Triple-Speed Ethernet Intel® FPGA IP Release Notes

Download PDF
ID 683215
Date 7/08/2024
Public
Document Table of Contents
Document Table of Contents x
1. Triple-Speed Ethernet Intel® FPGA IP (intel_eth_tse) Release Notes 2. Triple-Speed Ethernet Intel® FPGA IP (altera_eth_tse) Release Notes
1. Triple-Speed Ethernet Intel® FPGA IP (intel_eth_tse) Release Notes x
1.1. Triple-Speed Ethernet Intel® FPGA IP (intel_eth_tse) v5.0.0 1.2. Triple-Speed Ethernet Intel® FPGA IP (intel_eth_tse) v4.0.0
2. Triple-Speed Ethernet Intel® FPGA IP (altera_eth_tse) Release Notes x
2.1. Triple-Speed Ethernet Intel® FPGA IP v22.1.0 2.2. Triple-Speed Ethernet Intel® FPGA IP v22.0.0 2.3. Triple-Speed Ethernet Intel® FPGA IP v21.2.0 2.4. Triple-Speed Ethernet Intel® FPGA IP v21.1.0 2.5. Triple-Speed Ethernet Intel® FPGA IP v20.0.0 2.6. Triple-Speed Ethernet Intel® FPGA IP v19.5.0 2.7. Triple-Speed Ethernet Intel® FPGA IP v19.4.0 2.8. Triple-Speed Ethernet Intel® FPGA IP v19.2.0 2.9. Triple-Speed Ethernet Intel® FPGA IP v19.1 2.10. Triple-Speed Ethernet Intel® FPGA IP v18.0 2.11. Intel FPGA Triple Speed Ethernet IP Core v17.1 2.12. Triple Speed Ethernet IP Core v15.1 2.13. Triple Speed Ethernet IP Core v15.0 2.14. Triple Speed Ethernet IP Core v14.0 Arria 10 Edition 2.15. Triple Speed Ethernet IP Core v14.0 2.16. Triple Speed Ethernet IP Core v13.1 Arria 10 Edition 2.17. Triple Speed Ethernet IP Core v13.1 2.18. Triple-Speed Ethernet Intel® FPGA IP User Guide Archives 2.19. Triple-Speed Ethernet Stratix® 10 Intel® FPGA IP Design Example User Guide Archives
1. Triple-Speed Ethernet Intel® FPGA IP (intel_eth_tse) Release Notes
2. Triple-Speed Ethernet Intel® FPGA IP (altera_eth_tse) Release Notes

2.11. Intel FPGA Triple Speed Ethernet IP Core v17.1

Table 18.  v17.1 November 2017
Description Impact

Added support for the Stratix® 10, Cyclone® 10 GX, and Cyclone® 10 LP device families.

These devices are only available in Quartus® Prime Pro Edition software version 17.1 onwards.
In versions 17.0.2 and earlier of the Triple-Speed Ethernet IP core, the Triple-Speed Ethernet IP variant with LVDS I/O for PMA implementation in Arria® 10 devices may experience performance risk. This issue is fixed in the Quartus® Prime software version 17.1. To upgrade designs from previous versions of the Quartus® Prime software to version 17.1, you must regenerate the Triple-Speed Ethernet IP core and recompile the design in the Quartus® Prime software version 17.1. Refer to the KDB page for more information.
The number of ports supported for Triple-Speed Ethernet design with LVDS I/O targeting Stratix® 10, Arria® 10, and Cyclone® 10 GX is 8 per instance. You must not promote the reference clock to global clock manually. Assign the number of ports supported and its reference clock to the same I/O bank as inter-bank clock sharing is not allowed. —
RGMII interface is not supported in Stratix® 10, Arria® 10, and Cyclone® 10 GX devices. —
Related Information
Level Two Title