Accelerator Functional Unit Developer Guide: Intel FPGA Programmable Acceleration Card N3000 Variants

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ID 683190
Date 7/15/2022
Public
Document Table of Contents
Document Table of Contents x
1. About This Document 2. Introduction 3. High Level Description 4. Creating an N3000 FPGA Design 5. Capturing Signals in AFU with Signal Tap 6. Document Revision History for the Accelerator Functional Unit Developer Guide: Intel FPGA Programmable Acceleration Card N3000 Variants
1. About This Document x
1.1. Acronym List
2. Introduction x
2.1. Base Knowledge and Skills Prerequisites
2.1. Base Knowledge and Skills Prerequisites x
2.1.1. Considerations
3. High Level Description x
3.1. Steps for Creating Your AFU 3.2. N3000 Block Diagram 3.3. Factory Image Description
3.2. N3000 Block Diagram x
3.2.1. In-Line Data Path 3.2.2. Supported Ethernet Network Configurations 3.2.3. Provided Files 3.2.4. Internal Interfaces
3.2.3. Provided Files x
3.2.3.1. Directory Structure
3.2.4. Internal Interfaces x
3.2.4.1. Core Cache Interface (CCI-P) 3.2.4.2. Ethernet Interface 3.2.4.3. Ethernet MAC 3.2.4.4. 40G – 25G Gearbox 3.2.4.5. External Memory Interfaces 3.2.4.6. Ethernet MAC Wrapper Register Access
3.2.4.1. Core Cache Interface (CCI-P) x
3.2.4.1.1. FPGA Internal Register Access
3.2.4.5. External Memory Interfaces x
3.2.4.5.1. DDR4A and DDR4B 3.2.4.5.2. DDR4C 3.2.4.5.3. QDR4 Interface
4. Creating an N3000 FPGA Design x
4.1. Create New Project Directory 4.2. Create Your AFU Design Files 4.3. Build with make 4.4. Check Timing 4.5. Loading Your AFU into the Intel FPGA PAC N3000
4.2. Create Your AFU Design Files x
4.2.1. ccip_std_afu.sv 4.2.2. AFU File 4.2.3. QSF File 4.2.4. SDC File
4.5. Loading Your AFU into the Intel FPGA PAC N3000 x
4.5.1. Loading Your FPGA Image with JTAG 4.5.2. AFU Clocks 4.5.3. Creating an AFU with High Level Synthesis (HLS)
4.5.1. Loading Your FPGA Image with JTAG x
4.5.1.1. Preparing Your N3000 for JTAG 4.5.1.2. Disabling PCIe* Automatic Error Reporting (AER) 4.5.1.3. Using JTAG to Load the Intel® Arria® 10 *.sof file 4.5.1.4. How to Rescan PCIe* Bus and Re-enable PCIe* AER
4.5.2. AFU Clocks x
4.5.2.1. Hello AFU Example (uClk_usr) 4.5.2.2. Hello AFU Example (pll)
4.5.3. Creating an AFU with High Level Synthesis (HLS) x
4.5.3.1. Setting Up a Shell for HLS Development Work 4.5.3.2. Using the Initial Shell Design as a Shell 4.5.3.3. Compiling the Design and Producing a new N3000 FPGA Bitstream 4.5.3.4. Verifying Timing Constraints are Satisfied
5. Capturing Signals in AFU with Signal Tap x
5.1. Adding Signal Tap to the Design 5.2. Loading FPGA Image 5.3. Set Up Connections 5.4. How to Exit from the Debug Session 5.5. Troubleshooting Remote Debug Connections
1. About This Document
2. Introduction
3. High Level Description
4. Creating an N3000 FPGA Design
5. Capturing Signals in AFU with Signal Tap
6. Document Revision History for the Accelerator Functional Unit Developer Guide: Intel FPGA Programmable Acceleration Card N3000 Variants

5.2. Loading FPGA Image

  1. Change directories to the build directory where pac-n3000-secure-update-unsigned.bin was created by make and create an unsigned FPGA image using PACSign. Please note, this step assumes your target N3000 board has not had the root key programmed on the board. 
    $ cd prj/pac_baseline/build
  2. Before running PACSign, ensure you have the following environment setting: 
    export PYTHONPATH=/usr/local/lib/python3.6/site-packages/
  3. Create the image: 
    $ PACSign SR -t UPDATE -H openssl_manager  \
-i pac-n3000-secure-update-raw.bin  -o hello_afu_unsigned.bin
No root key specified.  Generate unsigned bitstream? Y = yes, N = no: y
No CSK specified.  Generate unsigned bitstream? Y = yes, N = no: y

    By responding with 'y', you are creating an unsigned binary file that can be loaded into a N3000 board that has not had the root key hash loaded into flash.

  4. Flash your N3000 image with this new file.
    Note: This command must be done as sudo or root. 
    $ sudo fpgasupdate hello_afu_unsigned.bin 3e:00.0
    Note: Your PCIe b:d.f value can be different from 3e:00.0 used above.

    This command takes about 40 minutes to complete.

  5. Perform a remote system update to load the new FPGA image using your PCIe B.D.f. 
    $ sudo rsu fpga 3e:00.0
  6. Verify the hello_afu_stp FPGA image is loaded with the fpgainfo port command showing the Accelerator Id as 850adcc2-6ceb-4b22-9722-d43375b61c66. 
    # fpgainfo port
Board Management Controller, MAX10 NIOS FW version D.2.0.19
Board Management Controller, MAX10 Build version D.2.0.6
//****** PORT ******//
Object Id : 0xED00000
PCIe s:b:d.f : 0000:3e:00.0
Device Id : 0x0b30
Numa Node : 1
Ports Num : 01
Bitstream Id : 0x21000410030509
Bitstream Version : 0.2.3
Pr Interface Id : a5d72a3c-c8b0-4939-912c-f715e5dc10ca
Accelerator Id : 850adcc2-6ceb-4b22-9722-d43375b61c66
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