Accelerator Functional Unit Developer Guide: Intel FPGA Programmable Acceleration Card N3000 Variants

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ID 683190
Date 7/15/2022
Public
Document Table of Contents
Document Table of Contents x
1. About This Document 2. Introduction 3. High Level Description 4. Creating an N3000 FPGA Design 5. Capturing Signals in AFU with Signal Tap 6. Document Revision History for the Accelerator Functional Unit Developer Guide: Intel FPGA Programmable Acceleration Card N3000 Variants
1. About This Document x
1.1. Acronym List
2. Introduction x
2.1. Base Knowledge and Skills Prerequisites
2.1. Base Knowledge and Skills Prerequisites x
2.1.1. Considerations
3. High Level Description x
3.1. Steps for Creating Your AFU 3.2. N3000 Block Diagram 3.3. Factory Image Description
3.2. N3000 Block Diagram x
3.2.1. In-Line Data Path 3.2.2. Supported Ethernet Network Configurations 3.2.3. Provided Files 3.2.4. Internal Interfaces
3.2.3. Provided Files x
3.2.3.1. Directory Structure
3.2.4. Internal Interfaces x
3.2.4.1. Core Cache Interface (CCI-P) 3.2.4.2. Ethernet Interface 3.2.4.3. Ethernet MAC 3.2.4.4. 40G – 25G Gearbox 3.2.4.5. External Memory Interfaces 3.2.4.6. Ethernet MAC Wrapper Register Access
3.2.4.1. Core Cache Interface (CCI-P) x
3.2.4.1.1. FPGA Internal Register Access
3.2.4.5. External Memory Interfaces x
3.2.4.5.1. DDR4A and DDR4B 3.2.4.5.2. DDR4C 3.2.4.5.3. QDR4 Interface
4. Creating an N3000 FPGA Design x
4.1. Create New Project Directory 4.2. Create Your AFU Design Files 4.3. Build with make 4.4. Check Timing 4.5. Loading Your AFU into the Intel FPGA PAC N3000
4.2. Create Your AFU Design Files x
4.2.1. ccip_std_afu.sv 4.2.2. AFU File 4.2.3. QSF File 4.2.4. SDC File
4.5. Loading Your AFU into the Intel FPGA PAC N3000 x
4.5.1. Loading Your FPGA Image with JTAG 4.5.2. AFU Clocks 4.5.3. Creating an AFU with High Level Synthesis (HLS)
4.5.1. Loading Your FPGA Image with JTAG x
4.5.1.1. Preparing Your N3000 for JTAG 4.5.1.2. Disabling PCIe* Automatic Error Reporting (AER) 4.5.1.3. Using JTAG to Load the Intel® Arria® 10 *.sof file 4.5.1.4. How to Rescan PCIe* Bus and Re-enable PCIe* AER
4.5.2. AFU Clocks x
4.5.2.1. Hello AFU Example (uClk_usr) 4.5.2.2. Hello AFU Example (pll)
4.5.3. Creating an AFU with High Level Synthesis (HLS) x
4.5.3.1. Setting Up a Shell for HLS Development Work 4.5.3.2. Using the Initial Shell Design as a Shell 4.5.3.3. Compiling the Design and Producing a new N3000 FPGA Bitstream 4.5.3.4. Verifying Timing Constraints are Satisfied
5. Capturing Signals in AFU with Signal Tap x
5.1. Adding Signal Tap to the Design 5.2. Loading FPGA Image 5.3. Set Up Connections 5.4. How to Exit from the Debug Session 5.5. Troubleshooting Remote Debug Connections
1. About This Document
2. Introduction
3. High Level Description
4. Creating an N3000 FPGA Design
5. Capturing Signals in AFU with Signal Tap
6. Document Revision History for the Accelerator Functional Unit Developer Guide: Intel FPGA Programmable Acceleration Card N3000 Variants

4.3. Build with make

The process of creating an N3000 FPGA image is simplified with the provided Makefile that automates the setting of compile parameters and combining your design files with the supplied source files. The Makefile flow starts with your design input files and ends after Intel® Quartus® Prime synthesizes and places the output and a binary FPGA file that is ready for secure signing with PACSign.

The make flow is only supported on Linux* platforms. Your development system requires the following:

Make:
  • make 3.81 (or newer)
Python:
  • Python 3.6
You invoke the make flow with the following command input syntax:
  • make [target] [options] [paths] [versioning]
Target—required, input only one:
  • 2x1x25G
  • 2x2x25G
  • 4x25G
  • 8x10G
  • 2x1x25Gx2FVL
  • 1x2x25G
  • clean
  • archive
Target archive stores whole database as a Quartus Archive (.qar) file.

Options

Option Value Description Required Default Comment
GUI 0 run selected stage NO 0
1 open Intel® Quartus® Prime GUI
SEED 0 - 232-1 fitter seed NO 1 Helpful in achieving timing closure
STAGE compile execute full flow (step-by-step) YES Not applicable
synthesis execute analysis and synthesis calls ipgenerate
fitter execute fitting (Fit, Place, Route) calls ipgenerate
fitter-timing execute fitter and timing analysis calls ipgenerate
analysis-timing execute timing analysis requires completed fitter
analysis-power execute power analysis requires completed fitter
assembler execute assembler requires completed fitter
ipgenerate generate IPs
dummy do nothing GUI only
USE_BBS_CLK 0 do not take user clock from BBS NO 0
1 take user clock from BBS Required if CCI-P clock uClk_usr or uClk_usrDiv2 is used in your design
INCLUDE_DIAGNOSTICS 0 exclude AFU diagnostics NO 1
1 include AFU diagnostics
INCLUDE_AFU_PCIE1 0 exclude AFU PCIe* 1 NO 1
1 include AFU PCIe* 1
INCLUDE_MEMORY 0 exclude all EMIFs NO 1
1 include all EMIFs
INCLUDE_DDR4_A 0 exclude DDR4 A NO INCLUDE_MEMORY
1 include DDR4 A
INCLUDE_DDR4_B 0 exclude DDR4 B NO INCLUDE_MEMORY
1 include DDR4 B
INCLUDE_DDR4_C 0 exclude DDR4 C NO INCLUDE_MEMORY
1 include DDR4 C
INCLUDE_QDR 0 exclude QDR NO INCLUDE_MEMORY
1 include QDR
MAC_LIGHTWEIGHT_MODE 0 disabled NO 0 Disabled non required features in MACs for less logic consumption
1 enabled
DATAPATH_MODE normal Ethernet aggregated mode NO normal
disaggregated disaggregated Ethernet mode
lightweight lightweight Ethernet mode
INCLUDE_SEU 0 Excludes SEU detection circuit NO 1
1 Includes SEU detection circuit
ARCHIVE_NAME [any string] .qar archive name for .qdb archive NO snapshot.qar used by archive target

Usage Examples:

1. Set up your shell environment to use N3000 provided Intel® Quartus® Prime 
$ source <N3000 Installation Directory>/inteldevstack/bin/init_env.sh
The example of the N3000 Make command runs the full compile process of the 2 x 2 x 25 GbE factory image using the command line (non-GUI) mode with fitter seed equal to 5: 
$ make 2x2x25G SEED=5 STAGE=compile
Note: Some designs may require multiple seed passes using seeds 1 to 8 to achieve timing closure. Also, the Design Space Explorer does not work with the N3000 make design flow.

Paths

Path Description Default
PROJECT_FILE main project qpf prj/pac_baseline/chip.qpf
PAC_ROOT N3000 sources root where main .qip is located hw/pac
AFU_ROOT AFU sources root where afu.qsf is located hw/afu/hw

Versioning

Versioning Description Default
PAC_VER_MAJOR SemVer Major. 0 - 15 0
PAC_VER_MINOR SemVer Minor. 0 – 255 0
PAC_VER_PATCH SemVer Patch. 0 – 15 0
REVISION_ID 32-bit 0
AFU_REVISION_ID 12-bit 0

Pr_Interface_ID

The OPAE tool fpgainfo lists the target configuration unique Pr_Interface_ID:
TARGET Pr_Interface_ID
8x10G 901DD697-CA79-4B05-B843-8138CEFA2846
4x25G F3C99413-5081-4AAD-BCED-07EB84A6D0BB
2x2x25G A5D72A3C-C8B0-4939-912C-F715E5DC10CA

The build process combines your afu.qsf file with a top level chip.qsf that includes external memory interfaces, MACs, and the encrypted CCI-P and management blocks.

To compile the hello_afu targeting the 2x2x25 network interface, execute the following in the top directory: 
$ cd $N3000_EXAMPLE_ROOT/hello_afu
$ make 2x2x25G GUI=1 INCLUDE_DIAGNOSTICS=0 INCLUDE_MEMORY=0 \ 
PAC_VER_MAJOR=3 PAC_VER_MINOR=5 PAC_VER_PATCH=6 \ 
REVISION_ID=12345678 INCLUDE_AFU_PCIE1=0

The following example steps use the Quartus GUI to illustrate the design flow. Once you are familiar with this flow you may prefer to use the non-GUI mode and additionally utilization of user created scripted or automated build flow.

This brings up the Intel® Quartus® Prime GUI. Click the Start Compilation play button.
Note: The Launch IP Upgrade Tool button appears. You can safely ignore this warning.

When your compile is complete, do not close Intel® Quartus® Prime, so that you can continue with the next steps.

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