Accelerator Functional Unit Developer Guide: Intel FPGA Programmable Acceleration Card N3000 Variants

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ID 683190
Date 7/15/2022
Public
Document Table of Contents
Document Table of Contents x
1. About This Document 2. Introduction 3. High Level Description 4. Creating an N3000 FPGA Design 5. Capturing Signals in AFU with Signal Tap 6. Document Revision History for the Accelerator Functional Unit Developer Guide: Intel FPGA Programmable Acceleration Card N3000 Variants
1. About This Document x
1.1. Acronym List
2. Introduction x
2.1. Base Knowledge and Skills Prerequisites
2.1. Base Knowledge and Skills Prerequisites x
2.1.1. Considerations
3. High Level Description x
3.1. Steps for Creating Your AFU 3.2. N3000 Block Diagram 3.3. Factory Image Description
3.2. N3000 Block Diagram x
3.2.1. In-Line Data Path 3.2.2. Supported Ethernet Network Configurations 3.2.3. Provided Files 3.2.4. Internal Interfaces
3.2.3. Provided Files x
3.2.3.1. Directory Structure
3.2.4. Internal Interfaces x
3.2.4.1. Core Cache Interface (CCI-P) 3.2.4.2. Ethernet Interface 3.2.4.3. Ethernet MAC 3.2.4.4. 40G – 25G Gearbox 3.2.4.5. External Memory Interfaces 3.2.4.6. Ethernet MAC Wrapper Register Access
3.2.4.1. Core Cache Interface (CCI-P) x
3.2.4.1.1. FPGA Internal Register Access
3.2.4.5. External Memory Interfaces x
3.2.4.5.1. DDR4A and DDR4B 3.2.4.5.2. DDR4C 3.2.4.5.3. QDR4 Interface
4. Creating an N3000 FPGA Design x
4.1. Create New Project Directory 4.2. Create Your AFU Design Files 4.3. Build with make 4.4. Check Timing 4.5. Loading Your AFU into the Intel FPGA PAC N3000
4.2. Create Your AFU Design Files x
4.2.1. ccip_std_afu.sv 4.2.2. AFU File 4.2.3. QSF File 4.2.4. SDC File
4.5. Loading Your AFU into the Intel FPGA PAC N3000 x
4.5.1. Loading Your FPGA Image with JTAG 4.5.2. AFU Clocks 4.5.3. Creating an AFU with High Level Synthesis (HLS)
4.5.1. Loading Your FPGA Image with JTAG x
4.5.1.1. Preparing Your N3000 for JTAG 4.5.1.2. Disabling PCIe* Automatic Error Reporting (AER) 4.5.1.3. Using JTAG to Load the Intel® Arria® 10 *.sof file 4.5.1.4. How to Rescan PCIe* Bus and Re-enable PCIe* AER
4.5.2. AFU Clocks x
4.5.2.1. Hello AFU Example (uClk_usr) 4.5.2.2. Hello AFU Example (pll)
4.5.3. Creating an AFU with High Level Synthesis (HLS) x
4.5.3.1. Setting Up a Shell for HLS Development Work 4.5.3.2. Using the Initial Shell Design as a Shell 4.5.3.3. Compiling the Design and Producing a new N3000 FPGA Bitstream 4.5.3.4. Verifying Timing Constraints are Satisfied
5. Capturing Signals in AFU with Signal Tap x
5.1. Adding Signal Tap to the Design 5.2. Loading FPGA Image 5.3. Set Up Connections 5.4. How to Exit from the Debug Session 5.5. Troubleshooting Remote Debug Connections
1. About This Document
2. Introduction
3. High Level Description
4. Creating an N3000 FPGA Design
5. Capturing Signals in AFU with Signal Tap
6. Document Revision History for the Accelerator Functional Unit Developer Guide: Intel FPGA Programmable Acceleration Card N3000 Variants

5.1. Adding Signal Tap to the Design

After you have compiled the hello_afu design, you can proceed as follows for adding Signal Tap to the design.
  1. Familiarize yourself with the project hierarchy. If your Project Navigator is not already in view in your main Intel® Quartus® Prime window, then in the Intel® Quartus® Prime window select View > Project Navigator. Detach the Project Navigator pane to expand its view. Expand the pac_top instance. Now expand the inst_green_bs instance. Next expand inst_ccip_std_afu. Your Project Navigator display should look as shown below:
  2. For this learning tutorial, the CCI-P interface and scratch register is instrumented. Select the afu instance in Project Navigator and right click, then select Locate Node and finally, Locate in Design File. See screen shot below:
  3. This brings up the hello_afu.sv SystemVerilog code. Having the code available for review while defining the signals to be instrumented is highly useful.
  4. Open the Signal Tap tool to create a *.stp file defining the signals to be instrumented. See example screen shot below on how to open the Signal Tap tool:
    1. The Signal Tap GUI appears as shown below:
    2. You can now set up a Signal Tap instance to instrument a portion of the design for observability.
      In this example, the Signal Tap instance is renamed to hello_afu to indicate its use to instrument the hello_afu module. To rename the auto_signaltap_0 instance, right click and select Rename Instance:
  5. For the hello_afu Signal Tap instance define the clock used to sample the signals to be instrumented. For accurate results, the instrumented signals must be in the domain of this clock. To select the clock, select the … button under “Signal Configuration”:
    1. This brings up the Node Finder tool. Find the “Look in:” listing go to the right and click … to bring up the “Select Hierarchy Level” viewer. See screen shot:
    2. In the Select Hierarchy Level viewer expand pac_top, inst_green_bs, inst_ccip_std_afu and select afu and click OK. See screen shot:
    3. From reviewing the hello_afu.sv code, notice all signals are synchronous to signal clk. In the Node Finder window, type in *clk* in the “Named” blank and click Search. Expand each instance selection in the “Matching Nodes” pane. Then select clk and the > to make this the signal used for clocking the Signal Tap instance. See screen shot:
      1. Press OK
      2. The Signal Configuration dock on the far right should look as shown below:
  6. You can increase the depth of the samples captured by increasing Sample depth. For this example, the depth is increased to 1 K. Please keep in mind, increased depth means more FPGA resources used for the Signal Tap instance.
  7. Select the signals to be added to the hello_afu Signal Tap instance by double clicking the Double-click to add nodes area of the “Setup” dock. This brings up the Node Finder tool. Repeat the steps above to set the “Look in:” box to narrow the search to just the hello_afu instance. You want to see the CCI-P interface signals and scratch pad register. Enter cp2af_sRxPort* in the "Named" entry field and click Search. Click the >> to select all signals to give you total visibility of the ccip RX bus input to the hello_afu. See screen shot below:
  8. Now change “Named:” to scratch* and click Search. Expand Matching Nodes until the scratch_reg is displayed. Select scratch_reg and then >> to add the scratch register signals to the “Nodes Found” list. See screen shot:
  9. Now enter af2cp_sTxPort* in the "Named" entry field and click Search to instrument the output CCI-P bus signals. Expand the instance names in “Matching Nodes". Do not select names ending in ~reg0. Your display should be as shown below:
  10. Click Insert and Close. Your display should be as shown below:
  11. Select File > Save As and save the newly created Signal Tap Logic Analyzer file as hello_afu.stp in the current directory.
  12. When asked: “Do you want to enable Signal Tap File hello_afu.stp for the current project?” Click Yes.
  13. Close the Signal Tap GUI.
  14. Re-Run a full compilation to create a new FPGA implementation with hello_afu Signal Tap instrumentation included.
  15. Once the build completes, the newly created pac-n3000-secure-update-unsigned.bin with Signal Tap instrumentation can be loaded into FPGA Flash for storage and use as the user image loaded into the Intel® Arria® 10 GT FPGA.
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