Accelerator Functional Unit Developer Guide: Intel FPGA Programmable Acceleration Card N3000 Variants

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ID 683190
Date 7/15/2022
Public
Document Table of Contents
Document Table of Contents x
1. About This Document 2. Introduction 3. High Level Description 4. Creating an N3000 FPGA Design 5. Capturing Signals in AFU with Signal Tap 6. Document Revision History for the Accelerator Functional Unit Developer Guide: Intel FPGA Programmable Acceleration Card N3000 Variants
1. About This Document x
1.1. Acronym List
2. Introduction x
2.1. Base Knowledge and Skills Prerequisites
2.1. Base Knowledge and Skills Prerequisites x
2.1.1. Considerations
3. High Level Description x
3.1. Steps for Creating Your AFU 3.2. N3000 Block Diagram 3.3. Factory Image Description
3.2. N3000 Block Diagram x
3.2.1. In-Line Data Path 3.2.2. Supported Ethernet Network Configurations 3.2.3. Provided Files 3.2.4. Internal Interfaces
3.2.3. Provided Files x
3.2.3.1. Directory Structure
3.2.4. Internal Interfaces x
3.2.4.1. Core Cache Interface (CCI-P) 3.2.4.2. Ethernet Interface 3.2.4.3. Ethernet MAC 3.2.4.4. 40G – 25G Gearbox 3.2.4.5. External Memory Interfaces 3.2.4.6. Ethernet MAC Wrapper Register Access
3.2.4.1. Core Cache Interface (CCI-P) x
3.2.4.1.1. FPGA Internal Register Access
3.2.4.5. External Memory Interfaces x
3.2.4.5.1. DDR4A and DDR4B 3.2.4.5.2. DDR4C 3.2.4.5.3. QDR4 Interface
4. Creating an N3000 FPGA Design x
4.1. Create New Project Directory 4.2. Create Your AFU Design Files 4.3. Build with make 4.4. Check Timing 4.5. Loading Your AFU into the Intel FPGA PAC N3000
4.2. Create Your AFU Design Files x
4.2.1. ccip_std_afu.sv 4.2.2. AFU File 4.2.3. QSF File 4.2.4. SDC File
4.5. Loading Your AFU into the Intel FPGA PAC N3000 x
4.5.1. Loading Your FPGA Image with JTAG 4.5.2. AFU Clocks 4.5.3. Creating an AFU with High Level Synthesis (HLS)
4.5.1. Loading Your FPGA Image with JTAG x
4.5.1.1. Preparing Your N3000 for JTAG 4.5.1.2. Disabling PCIe* Automatic Error Reporting (AER) 4.5.1.3. Using JTAG to Load the Intel® Arria® 10 *.sof file 4.5.1.4. How to Rescan PCIe* Bus and Re-enable PCIe* AER
4.5.2. AFU Clocks x
4.5.2.1. Hello AFU Example (uClk_usr) 4.5.2.2. Hello AFU Example (pll)
4.5.3. Creating an AFU with High Level Synthesis (HLS) x
4.5.3.1. Setting Up a Shell for HLS Development Work 4.5.3.2. Using the Initial Shell Design as a Shell 4.5.3.3. Compiling the Design and Producing a new N3000 FPGA Bitstream 4.5.3.4. Verifying Timing Constraints are Satisfied
5. Capturing Signals in AFU with Signal Tap x
5.1. Adding Signal Tap to the Design 5.2. Loading FPGA Image 5.3. Set Up Connections 5.4. How to Exit from the Debug Session 5.5. Troubleshooting Remote Debug Connections
1. About This Document
2. Introduction
3. High Level Description
4. Creating an N3000 FPGA Design
5. Capturing Signals in AFU with Signal Tap
6. Document Revision History for the Accelerator Functional Unit Developer Guide: Intel FPGA Programmable Acceleration Card N3000 Variants

3.1. Steps for Creating Your AFU

The following steps are suggested for designing a custom FPGA application for the N3000:

  1. Become familiar with the board and FPGA block diagrams, interfaces and code provided within the N3000 factory image.
  2. Review the Intel® Acceleration Stack for Intel® Xeon® CPU with FPGAs Core Cache Interface (CCI-P) Reference Manual. You must follow the interface requirements and include required registers in your design for proper N3000 operation.
    In addition, the OPAE Basic Building Blocks wiki provides CCI-P tutorials and basic building blocks (BBB) for interfacing your AFU. You are strongly encouraged to review this resource. The Memory Properties Factory BBB is an essential component for transaction ordering in AFUs requiring more complex host interfacing functions.
  3. Define and plan your FPGA application.
  4. Copy the Initial_Shell_AFU files and directory structure. This directory structure is the starting point for your design.
  5. Implement your FPGA application. You can use one or a combination of the following design entry methods:
    1. RTL (System Verilog/VHDL)
    2. Platform Designer
    3. HLS
    Note: Existing design blocks can be added as required.
  6. Implement host software code.
  7. Simulate your design at the unit level.
  8. Create timing constraints files.
  9. Update the Intel® Quartus® Prime Settings File (afu.qsf) to add your new blocks.
  10. Compile, synthesize, place and route your new design using provided makefile.
  11. Validate timing closure.
  12. Validate power consumption.
  13. The provided makefile compilation script includes a post-compilation script that creates a raw binary file.
  14. The raw binary file is used as an input to the Intel® Acceleration Stack utility PACSign. PACSign adds a required header to the raw binary file. The output file from PACSign is validated by the N3000 Intel® MAX® 10 Root of Trust for storage in the N3000 flash storage.
  15. Flash the binary file produced by PACSign into FPGA flash using fpgasupdate.
  16. Use the rsu utility to load the new FPGA binary file from flash into the FPGA.
  17. If needed, use the Signal Tap tool to diagnose and resolve issues.
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