Accelerator Functional Unit Developer Guide: Intel FPGA Programmable Acceleration Card N3000 Variants

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ID 683190
Date 7/15/2022
Public
Document Table of Contents
Document Table of Contents x
1. About This Document 2. Introduction 3. High Level Description 4. Creating an N3000 FPGA Design 5. Capturing Signals in AFU with Signal Tap 6. Document Revision History for the Accelerator Functional Unit Developer Guide: Intel FPGA Programmable Acceleration Card N3000 Variants
1. About This Document x
1.1. Acronym List
2. Introduction x
2.1. Base Knowledge and Skills Prerequisites
2.1. Base Knowledge and Skills Prerequisites x
2.1.1. Considerations
3. High Level Description x
3.1. Steps for Creating Your AFU 3.2. N3000 Block Diagram 3.3. Factory Image Description
3.2. N3000 Block Diagram x
3.2.1. In-Line Data Path 3.2.2. Supported Ethernet Network Configurations 3.2.3. Provided Files 3.2.4. Internal Interfaces
3.2.3. Provided Files x
3.2.3.1. Directory Structure
3.2.4. Internal Interfaces x
3.2.4.1. Core Cache Interface (CCI-P) 3.2.4.2. Ethernet Interface 3.2.4.3. Ethernet MAC 3.2.4.4. 40G – 25G Gearbox 3.2.4.5. External Memory Interfaces 3.2.4.6. Ethernet MAC Wrapper Register Access
3.2.4.1. Core Cache Interface (CCI-P) x
3.2.4.1.1. FPGA Internal Register Access
3.2.4.5. External Memory Interfaces x
3.2.4.5.1. DDR4A and DDR4B 3.2.4.5.2. DDR4C 3.2.4.5.3. QDR4 Interface
4. Creating an N3000 FPGA Design x
4.1. Create New Project Directory 4.2. Create Your AFU Design Files 4.3. Build with make 4.4. Check Timing 4.5. Loading Your AFU into the Intel FPGA PAC N3000
4.2. Create Your AFU Design Files x
4.2.1. ccip_std_afu.sv 4.2.2. AFU File 4.2.3. QSF File 4.2.4. SDC File
4.5. Loading Your AFU into the Intel FPGA PAC N3000 x
4.5.1. Loading Your FPGA Image with JTAG 4.5.2. AFU Clocks 4.5.3. Creating an AFU with High Level Synthesis (HLS)
4.5.1. Loading Your FPGA Image with JTAG x
4.5.1.1. Preparing Your N3000 for JTAG 4.5.1.2. Disabling PCIe* Automatic Error Reporting (AER) 4.5.1.3. Using JTAG to Load the Intel® Arria® 10 *.sof file 4.5.1.4. How to Rescan PCIe* Bus and Re-enable PCIe* AER
4.5.2. AFU Clocks x
4.5.2.1. Hello AFU Example (uClk_usr) 4.5.2.2. Hello AFU Example (pll)
4.5.3. Creating an AFU with High Level Synthesis (HLS) x
4.5.3.1. Setting Up a Shell for HLS Development Work 4.5.3.2. Using the Initial Shell Design as a Shell 4.5.3.3. Compiling the Design and Producing a new N3000 FPGA Bitstream 4.5.3.4. Verifying Timing Constraints are Satisfied
5. Capturing Signals in AFU with Signal Tap x
5.1. Adding Signal Tap to the Design 5.2. Loading FPGA Image 5.3. Set Up Connections 5.4. How to Exit from the Debug Session 5.5. Troubleshooting Remote Debug Connections
1. About This Document
2. Introduction
3. High Level Description
4. Creating an N3000 FPGA Design
5. Capturing Signals in AFU with Signal Tap
6. Document Revision History for the Accelerator Functional Unit Developer Guide: Intel FPGA Programmable Acceleration Card N3000 Variants

4.5.1.2. Disabling PCIe* Automatic Error Reporting (AER)

When you program the FPGA using JTAG, the Intel® Arria® 10 PCIe* link goes down for a moment causing a server surprise link down event. To prevent this server event, temporarily disable the PCIe* AER for the N3000 PCIe* slot using the following steps:
  1. Find and record your N3000 PCIe* s:b:d.f value. You will use this PCIe* s:b:d.f value later for removing the N3000 from the PCIe* bus. In this example, use this value: 0000:08:00.0. 
    $ sudo fpgainfo fme
Board Management Controller, MAX10 NIOS FW version D.2.0.19
Board Management Controller, MAX10 Build version D.2.0.6
//****** FME ******//
Object Id                     : 0xF200000
PCIe s:b:d.f                  : 0000:08:00.0
Device Id                     : 0x0b30
Numa Node                     : 0
Ports Num                     : 01
Bitstream Id                  : 0x23000410010309
Bitstream Version             : 0.2.3
Pr Interface Id               : a5d72a3c-c8b0-4939-912c-f715e5dc10ca
Boot Page                     : user
  2. Use the command find_RP.sh to get board root PCIe* s:b:d.f . 
    $ cd <N3000 Install Directory>/N3000_supplemental_files/
$ ./find_RP.sh 
0000:00:03.0                     ----- >>> This is root port, take note of this value
0000:03:00.0
0000:04:09.0
0000:08:00.0 -> intel-fpga-dev.0
  3. The first entry in the list is the PCIe* Root port. In this example, 0000:00:03.0 is the root port. Your values may be different. The last entry is intel-fpga-dev.0.
  4. Using the root port, find the current AER settings and record the value. Use this value when you re-enable AER. 
    $ sudo setpci -s 0000:00:03.0 ECAP_AER+0x08.L 
00000000
$ sudo setpci -s 0000:00:03.0 ECAP_AER+0x14.L
00002000
  5. Disable AER for the root port: 
    $ sudo setpci -s 0000:00:03.0 ECAP_AER+0x08.L=0xffffffff
$ sudo setpci -s 0000:00:03.0 ECAP_AER+0x14.L=0xffffffff
  6. Using your board PCIe* s:b:d.f , remove the N3000 from the PCIe* bus. If using RHEL, you must enter the command as root: 
    # sudo echo 1 > /sys/bus/pci/devices/0000:08:00.0/remove
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