Accelerator Functional Unit Developer Guide: Intel FPGA Programmable Acceleration Card N3000 Variants

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ID 683190
Date 7/15/2022
Public
Document Table of Contents
Document Table of Contents x
1. About This Document 2. Introduction 3. High Level Description 4. Creating an N3000 FPGA Design 5. Capturing Signals in AFU with Signal Tap 6. Document Revision History for the Accelerator Functional Unit Developer Guide: Intel FPGA Programmable Acceleration Card N3000 Variants
1. About This Document x
1.1. Acronym List
2. Introduction x
2.1. Base Knowledge and Skills Prerequisites
2.1. Base Knowledge and Skills Prerequisites x
2.1.1. Considerations
3. High Level Description x
3.1. Steps for Creating Your AFU 3.2. N3000 Block Diagram 3.3. Factory Image Description
3.2. N3000 Block Diagram x
3.2.1. In-Line Data Path 3.2.2. Supported Ethernet Network Configurations 3.2.3. Provided Files 3.2.4. Internal Interfaces
3.2.3. Provided Files x
3.2.3.1. Directory Structure
3.2.4. Internal Interfaces x
3.2.4.1. Core Cache Interface (CCI-P) 3.2.4.2. Ethernet Interface 3.2.4.3. Ethernet MAC 3.2.4.4. 40G – 25G Gearbox 3.2.4.5. External Memory Interfaces 3.2.4.6. Ethernet MAC Wrapper Register Access
3.2.4.1. Core Cache Interface (CCI-P) x
3.2.4.1.1. FPGA Internal Register Access
3.2.4.5. External Memory Interfaces x
3.2.4.5.1. DDR4A and DDR4B 3.2.4.5.2. DDR4C 3.2.4.5.3. QDR4 Interface
4. Creating an N3000 FPGA Design x
4.1. Create New Project Directory 4.2. Create Your AFU Design Files 4.3. Build with make 4.4. Check Timing 4.5. Loading Your AFU into the Intel FPGA PAC N3000
4.2. Create Your AFU Design Files x
4.2.1. ccip_std_afu.sv 4.2.2. AFU File 4.2.3. QSF File 4.2.4. SDC File
4.5. Loading Your AFU into the Intel FPGA PAC N3000 x
4.5.1. Loading Your FPGA Image with JTAG 4.5.2. AFU Clocks 4.5.3. Creating an AFU with High Level Synthesis (HLS)
4.5.1. Loading Your FPGA Image with JTAG x
4.5.1.1. Preparing Your N3000 for JTAG 4.5.1.2. Disabling PCIe* Automatic Error Reporting (AER) 4.5.1.3. Using JTAG to Load the Intel® Arria® 10 *.sof file 4.5.1.4. How to Rescan PCIe* Bus and Re-enable PCIe* AER
4.5.2. AFU Clocks x
4.5.2.1. Hello AFU Example (uClk_usr) 4.5.2.2. Hello AFU Example (pll)
4.5.3. Creating an AFU with High Level Synthesis (HLS) x
4.5.3.1. Setting Up a Shell for HLS Development Work 4.5.3.2. Using the Initial Shell Design as a Shell 4.5.3.3. Compiling the Design and Producing a new N3000 FPGA Bitstream 4.5.3.4. Verifying Timing Constraints are Satisfied
5. Capturing Signals in AFU with Signal Tap x
5.1. Adding Signal Tap to the Design 5.2. Loading FPGA Image 5.3. Set Up Connections 5.4. How to Exit from the Debug Session 5.5. Troubleshooting Remote Debug Connections
1. About This Document
2. Introduction
3. High Level Description
4. Creating an N3000 FPGA Design
5. Capturing Signals in AFU with Signal Tap
6. Document Revision History for the Accelerator Functional Unit Developer Guide: Intel FPGA Programmable Acceleration Card N3000 Variants

3.2.4.1. Core Cache Interface (CCI-P)

The N3000 uses the CCI-P interface for compatibility with the OPAE software stack and drivers. The N3000 has the FIU capabilities of the Intel® PAC with Intel® Arria® 10 GX FPGA as shown in the Comparison of FIU Capabilities section of the Intel® Acceleration Stack for Intel® Xeon® CPU with FPGAs Core Cache Interface (CCI-P) Reference Manual.
Note: You must develop a detailed understanding of the CCI-P Interface as described in the CCI-P Interface section of the Intel® Acceleration Stack for Intel® Xeon® CPU with FPGAs Core Cache Interface (CCI-P) Reference Manual.

The N3000 has the following signals in the CCI-P interface:

Signal Width Direction Description

pClk

1

Input

200 MHz system clock. All CCI-P signals are synchronous to this signal.

pClkDiv2

1

Input

200 MHz system clock. This signal is a copy of pClk. Please ignore name

pClkDiv4

1

Input

200 MHz system clock. This signal is a copy of pClk. Please ignore name.

uClk_usr

1

Input

User clock – Default = 312.5 MHz clock. To use this clock, set USE_BBS_CLK=1 in make settings.

uClk_usrDiv2

1

Input

User clock – Default = 156.25 MHz clock. To use this clock, set USE_BBS_CLK=1 in make settings.

G_CLK100

1

Input

100 MHz global reference clock, for optional PCIe* IP core or additional PLLs if needed

t_if_ccip_Rx

struc

Input

CCI-P data input structure defined in ccip_if_pkg.sv

t_if_ccip_Tx

struc

Output

CCI-P data output structure defined in ccip_if_pkg.sv

pck_cp2af_softReset

1

Input

Active high reset. Synchronous with pClk asserted for 256 clock cycles.

pck_cp2af_pwrState

2

Input

Present, but not used

pck_cp2af_error

1

Input

Present, but not used

The CCI-P clocks: pClk, pClkDiv2, pClkDiv4, uClk_usr, and uClk_usrDiv2 do not allow you to change frequencies. If your AFU requires a different clock frequency, then instantiate a new PLL and use the G_CLK100 as a PLL reference clock.


Section Content
FPGA Internal Register Access

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