Accelerator Functional Unit Developer Guide: Intel FPGA Programmable Acceleration Card N3000 Variants

Download PDF
ID 683190
Date 7/15/2022
Public
Document Table of Contents
Document Table of Contents x
1. About This Document 2. Introduction 3. High Level Description 4. Creating an N3000 FPGA Design 5. Capturing Signals in AFU with Signal Tap 6. Document Revision History for the Accelerator Functional Unit Developer Guide: Intel FPGA Programmable Acceleration Card N3000 Variants
1. About This Document x
1.1. Acronym List
2. Introduction x
2.1. Base Knowledge and Skills Prerequisites
2.1. Base Knowledge and Skills Prerequisites x
2.1.1. Considerations
3. High Level Description x
3.1. Steps for Creating Your AFU 3.2. N3000 Block Diagram 3.3. Factory Image Description
3.2. N3000 Block Diagram x
3.2.1. In-Line Data Path 3.2.2. Supported Ethernet Network Configurations 3.2.3. Provided Files 3.2.4. Internal Interfaces
3.2.3. Provided Files x
3.2.3.1. Directory Structure
3.2.4. Internal Interfaces x
3.2.4.1. Core Cache Interface (CCI-P) 3.2.4.2. Ethernet Interface 3.2.4.3. Ethernet MAC 3.2.4.4. 40G – 25G Gearbox 3.2.4.5. External Memory Interfaces 3.2.4.6. Ethernet MAC Wrapper Register Access
3.2.4.1. Core Cache Interface (CCI-P) x
3.2.4.1.1. FPGA Internal Register Access
3.2.4.5. External Memory Interfaces x
3.2.4.5.1. DDR4A and DDR4B 3.2.4.5.2. DDR4C 3.2.4.5.3. QDR4 Interface
4. Creating an N3000 FPGA Design x
4.1. Create New Project Directory 4.2. Create Your AFU Design Files 4.3. Build with make 4.4. Check Timing 4.5. Loading Your AFU into the Intel FPGA PAC N3000
4.2. Create Your AFU Design Files x
4.2.1. ccip_std_afu.sv 4.2.2. AFU File 4.2.3. QSF File 4.2.4. SDC File
4.5. Loading Your AFU into the Intel FPGA PAC N3000 x
4.5.1. Loading Your FPGA Image with JTAG 4.5.2. AFU Clocks 4.5.3. Creating an AFU with High Level Synthesis (HLS)
4.5.1. Loading Your FPGA Image with JTAG x
4.5.1.1. Preparing Your N3000 for JTAG 4.5.1.2. Disabling PCIe* Automatic Error Reporting (AER) 4.5.1.3. Using JTAG to Load the Intel® Arria® 10 *.sof file 4.5.1.4. How to Rescan PCIe* Bus and Re-enable PCIe* AER
4.5.2. AFU Clocks x
4.5.2.1. Hello AFU Example (uClk_usr) 4.5.2.2. Hello AFU Example (pll)
4.5.3. Creating an AFU with High Level Synthesis (HLS) x
4.5.3.1. Setting Up a Shell for HLS Development Work 4.5.3.2. Using the Initial Shell Design as a Shell 4.5.3.3. Compiling the Design and Producing a new N3000 FPGA Bitstream 4.5.3.4. Verifying Timing Constraints are Satisfied
5. Capturing Signals in AFU with Signal Tap x
5.1. Adding Signal Tap to the Design 5.2. Loading FPGA Image 5.3. Set Up Connections 5.4. How to Exit from the Debug Session 5.5. Troubleshooting Remote Debug Connections
1. About This Document
2. Introduction
3. High Level Description
4. Creating an N3000 FPGA Design
5. Capturing Signals in AFU with Signal Tap
6. Document Revision History for the Accelerator Functional Unit Developer Guide: Intel FPGA Programmable Acceleration Card N3000 Variants

3.2.2. Supported Ethernet Network Configurations

The N3000 has three network configurations:
Network Configuration QSFP28 A QSFP28 B Intel® XL710 #1 Intel® XL710 #2 Supported Board OPN
8 x 10GbE 4 x 10GbE 4 x 10GbE 4 x 10GbE 4 x 10GbE BD-NFV-N3000-1
2 x 2 x 25GbE 2 x 25GbE 2 x 25GbE 2 x 40GbE 2 x 40GbE

BD-NFV-N3000-2

BD-NFV-N3000-N
4 x 25GbE 4 x 25GbE Not Used 2 x 40GbE 2 x 40GbE

BD-NFV-N3000-2

BD-NFV-N3000-N
  • 2 – QSFP ports where each QSFP supports 4 – 10 GbE lanes – this configuration is referred to as 8 X 10 G
  • 2 – QSFP slots where each QSFP supports 2 – 25 GbE lanes – this configuration is referred to as 2 x 2 x 25 G
  • 1 – QSFP port where 4 – 25 GbE lanes are supported. This configuration is referred to as 4 x 25 G
Note: The above network configurations are the only ones supported.

The fpga_top block contains a Nios® II processor and firmware that configures the network settings for the Intel® C827 Ethernet re-timer device. This Nios® II firmware is not user editable.

The Intel® Ethernet Controller XL710-BM2 network interface controller (NIC) is configured during board manufacturing to be either 10G or 40G. You cannot change the Intel® Ethernet Controller XL710-BM2 NIC to switch between 10G and 40G. If your data path requires the Intel® Ethernet Controller XL710-BM2 NIC, then you cannot switch between 10G and 25G network configurations. You can switch FPGA images between any of the supported network configurations.

Level Two Title