Accelerator Functional Unit Developer Guide: Intel FPGA Programmable Acceleration Card N3000 Variants

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ID 683190
Date 7/15/2022
Public
Document Table of Contents
Document Table of Contents x
1. About This Document 2. Introduction 3. High Level Description 4. Creating an N3000 FPGA Design 5. Capturing Signals in AFU with Signal Tap 6. Document Revision History for the Accelerator Functional Unit Developer Guide: Intel FPGA Programmable Acceleration Card N3000 Variants
1. About This Document x
1.1. Acronym List
2. Introduction x
2.1. Base Knowledge and Skills Prerequisites
2.1. Base Knowledge and Skills Prerequisites x
2.1.1. Considerations
3. High Level Description x
3.1. Steps for Creating Your AFU 3.2. N3000 Block Diagram 3.3. Factory Image Description
3.2. N3000 Block Diagram x
3.2.1. In-Line Data Path 3.2.2. Supported Ethernet Network Configurations 3.2.3. Provided Files 3.2.4. Internal Interfaces
3.2.3. Provided Files x
3.2.3.1. Directory Structure
3.2.4. Internal Interfaces x
3.2.4.1. Core Cache Interface (CCI-P) 3.2.4.2. Ethernet Interface 3.2.4.3. Ethernet MAC 3.2.4.4. 40G – 25G Gearbox 3.2.4.5. External Memory Interfaces 3.2.4.6. Ethernet MAC Wrapper Register Access
3.2.4.1. Core Cache Interface (CCI-P) x
3.2.4.1.1. FPGA Internal Register Access
3.2.4.5. External Memory Interfaces x
3.2.4.5.1. DDR4A and DDR4B 3.2.4.5.2. DDR4C 3.2.4.5.3. QDR4 Interface
4. Creating an N3000 FPGA Design x
4.1. Create New Project Directory 4.2. Create Your AFU Design Files 4.3. Build with make 4.4. Check Timing 4.5. Loading Your AFU into the Intel FPGA PAC N3000
4.2. Create Your AFU Design Files x
4.2.1. ccip_std_afu.sv 4.2.2. AFU File 4.2.3. QSF File 4.2.4. SDC File
4.5. Loading Your AFU into the Intel FPGA PAC N3000 x
4.5.1. Loading Your FPGA Image with JTAG 4.5.2. AFU Clocks 4.5.3. Creating an AFU with High Level Synthesis (HLS)
4.5.1. Loading Your FPGA Image with JTAG x
4.5.1.1. Preparing Your N3000 for JTAG 4.5.1.2. Disabling PCIe* Automatic Error Reporting (AER) 4.5.1.3. Using JTAG to Load the Intel® Arria® 10 *.sof file 4.5.1.4. How to Rescan PCIe* Bus and Re-enable PCIe* AER
4.5.2. AFU Clocks x
4.5.2.1. Hello AFU Example (uClk_usr) 4.5.2.2. Hello AFU Example (pll)
4.5.3. Creating an AFU with High Level Synthesis (HLS) x
4.5.3.1. Setting Up a Shell for HLS Development Work 4.5.3.2. Using the Initial Shell Design as a Shell 4.5.3.3. Compiling the Design and Producing a new N3000 FPGA Bitstream 4.5.3.4. Verifying Timing Constraints are Satisfied
5. Capturing Signals in AFU with Signal Tap x
5.1. Adding Signal Tap to the Design 5.2. Loading FPGA Image 5.3. Set Up Connections 5.4. How to Exit from the Debug Session 5.5. Troubleshooting Remote Debug Connections
1. About This Document
2. Introduction
3. High Level Description
4. Creating an N3000 FPGA Design
5. Capturing Signals in AFU with Signal Tap
6. Document Revision History for the Accelerator Functional Unit Developer Guide: Intel FPGA Programmable Acceleration Card N3000 Variants

4.5.3.2. Using the Initial Shell Design as a Shell

The Intel® N3000 Acceleration Stack for Development provides the Initial_Shell_Design as a starting point for your created designs. The Initial_Shell_Design is used as a shell for inclusion of the HLS AFU example.

  1. Copy the provided Initial_Shell_Design to a new directory for your tutorial work. 
    $ mkdir hls_example
$ cd hls_example
$ cp -R $N3000_EXAMPLE_ROOT/Initial_Shell_AFU/*
  2. Copy the Intel® provided HLS AFU example .tar file to your hls_example/hw directory and untar 
    $ cp  <Download directory>/hls_afu_2019-04-30.tar hls_example/hw/.
$ cd hls_example/hw
$ tar xf hls_afu_2019-04-30.tar
$ cd hls_afu/hw/rtl/hls
  3. Build and emulate the design using x86 instructions and run these commands: 
    $ make test-x86-64
i++ src/hls_afu.cpp src/test.cpp   --fp-relaxed -ghdl  -march=x86-64 -o test-x86-64
+--------------------------------------------+
| Run ./test-x86-64 <n> to execute the test. |
| <n> is 0, 1, or 2 depending on desired     |
| test behavior:                             |
|         <n> | effect                       |
|       ------+--------------------          |
|          0  | test both (default)          |
|          1  | test ac_int only             |
|          2  | test float only              |
+--------------------------------------------+
 
    $ ./test-x86-64 
Control which component gets tested by passing an integer!
arg   | effect              
------+-------------------- 
   0  | test both (default) 
   1  | test ac_int only    
   2  | test float only     
test AC_INT version and FLOAT version
 
AC_INT COMPONENT - 81 ELEMENTS
ac_inc:
sizeof(uint512) = 64 (64)
number of 512 bit (64-byte) numbers: 6
PASS
 
FLOATING-POINT COMPONENT - 81 ELEMENTS
fp_inc:
PASS
OVERALL:
PASSED
  4. Generate RTL and simulate the generated RTL with the ModelSim simulator: 
    $ make test-fpga
$ ./test-fpga
Control which component gets tested by passing an integer!
arg   | effect              
------+-------------------- 
   0  | test both (default) 
   1  | test ac_int only    
   2  | test float only     
test AC_INT version and FLOAT version
 
AC_INT COMPONENT - 81 ELEMENTS
ac_inc:
sizeof(uint512) = 64 (64)
number of 512 bit (64-byte) numbers: 6
PASS
 
FLOATING-POINT COMPONENT - 81 ELEMENTS
fp_inc:
PASS
OVERALL:
PASSED
  5. Confirm that the outputs from the test-x86-64 command and the test-fpga command match.

    The test-x86-64 command runs C++ code on the processor, while the test-fpga command compiles the C++ source to Verilog RTL and then simulates the generated RTL using the testbench defined in the code.

    For instructions about how to view the waveforms for this component, see the Intel® High Level Synthesis Compiler User Guide.

  6. Navigate to the qsys directory and open the system using Platform Designer. 
    $ cd ../qsys
$ qsys-edit hls_afu_container.qsys
    In the Open System dialog box, select None for the Quartus project dropdown.
    Figure 39. Open System GUI
    Note: You can safely ignore the device part number for this example.
  7. Click Open.
  8. Click Close on the Open System Completed pop up.
  9. To reload the system and ensure that all search paths are correct, click on Validate System Integrity at the bottom of the Platform Designer window.
  10. After Validate System Integrity successfully completes, click Close. Investigate connectivity of Platform Designer components.
    Figure 40. System View GUI
  11. Generate HDL by clicking Generate HDL, then in Generation pop up, click Generate and Save Changes. You may safely ignore warnings. Click Close.
    Figure 41. Generate Completed GUI
  12. Exit Platform Designer and change directory to the hw/hls_afu/hw/rtl directory and verify contents: 
    $ cd ..
$ ls
afu.sv  BBB_cci_mpf  BBB_ccip_avmm  cci-if  ccip_interface_reg.sv  ccip_std_afu.sv  filelist.txt  hls  hls_afu.json  pcie  qsys

    The N3000 does not support Intel® AFU Simulation Environment (ASE) for co-simulation of AFU RTL and host software.

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