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4.5.3.3. Compiling the Design and Producing a new N3000 FPGA Bitstream
To compile the design and produce a new N3000 FPGA bitstream, perform the following steps:
- Copy the cci-if and pcie directories to the hw/hls_afu/hw/rtl directory
$ cp -R ../../../afu/hw/rtl/cci-if . $ cp -R ../../../afu/hw/rtl/pcie .The cci-if and pcie directories were included in the Intial_Shell_Desgin and these directories are needed to compile the HLS AFU example.
- The HLS Example provides an ccip_std_afu.sv file that is based on the N3000. You must update the ccip_std_afu.sv file with N3000 interfaces. The updated code is shown below:
// *************************************************************************** // Copyright (c) 2013-2016, Intel Corporation // // Redistribution and use in source and binary forms, with or without // modification, are permitted provided that the following conditions are met: // // * Redistributions of source code must retain the above copyright notice, // this list of conditions and the following disclaimer. // * Redistributions in binary form must reproduce the above copyright notice, // this list of conditions and the following disclaimer in the documentation // and/or other materials provided with the distribution. // * Neither the name of Intel Corporation nor the names of its contributors // may be used to endorse or promote products derived from this software // without specific prior written permission. // // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" // AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE // IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE // ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE // LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR // CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF // SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS // INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN // CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) // ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE // POSSIBILITY OF SUCH DAMAGE. // // Module Name : ccip_std_afu // Project : ccip afu top // Description : This module instantiates CCI-P compliant AFU // *************************************************************************** // Include MPF data types, including the CCI interface pacakge. //import ccip_if_pkg::*; `include "cci_mpf_if.vh" import cci_mpf_csrs_pkg::*; module ccip_std_afu #( parameter UPL_VERSION = 32'h2019_0905, parameter LOG2_DP_DATA_PATH1_WIDTH = 9, parameter LOG2_DP_DATA_PATH0_WIDTH = 9, parameter DP_CHA_WIDTH = 2, parameter NUM_AVST_IF_LINE = 2, parameter NUM_AVST_IF_FVL = 2, parameter LOG2_MAC_DATA_WIDTH = 6, parameter USR_ERROR_WIDTH = 1, parameter LIGHTWEIGHT_MODE = 0, parameter TIMESTAMP_PASS = 0, parameter int TIMESTAMP_WIDTH = 96 ) ( input logic G_CLK100,// 100MHz global reference clock input logic pClk, // 400MHz - CCI-P clock domain. Primary interface clock input logic pClkDiv2, // not used. input logic pClkDiv4, // not used. input logic uClk_usr, // User clock domain. Refer to clock programming guide input logic uClk_usrDiv2, // User clock domain. Half the programmed frequency input logic pck_cp2af_softReset, // CCI-P ACTIVE HIGH Soft Reset input logic [1:0] pck_cp2af_pwrState, // CCI-P AFU Power State input logic pck_cp2af_error, // CCI-P Protocol Error Detected // Interface structures input t_if_ccip_Rx pck_cp2af_sRx, // CCI-P Rx Port output t_if_ccip_Tx pck_af2cp_sTx, // CCI-P Tx Port input logic pcie1_pipe_gen3_x8_ref_clk, input logic pcie1_pcie_pins_perst_n, input logic [7:0] pcie1_pipe_gen3_x8_rx_serial, output logic [7:0] pcie1_pipe_gen3_x8_tx_serial, input logic ing_egr_clock, output logic fvl_40g_bp [NUM_AVST_IF_LINE], output logic [1:0] mac2_10g_avalon_st_pause_data[NUM_AVST_IF_LINE], output logic [1:0] mac_10g_avalon_st_pause_data [NUM_AVST_IF_LINE], input logic ing_in_clk[NUM_AVST_IF_LINE], input logic ing_in_rst[NUM_AVST_IF_LINE], input logic [USR_ERROR_WIDTH-1:0] ing_in_err[NUM_AVST_IF_LINE], input logic ing_in_val[NUM_AVST_IF_LINE], input logic ing_in_sop[NUM_AVST_IF_LINE], input logic ing_in_eop[NUM_AVST_IF_LINE], input logic [2**LOG2_DP_DATA_PATH0_WIDTH - 1:0] ing_in_dat[NUM_AVST_IF_LINE], input logic [(LOG2_DP_DATA_PATH0_WIDTH-3) -1:0] ing_in_mty[NUM_AVST_IF_LINE], output logic ing_in_rdy[NUM_AVST_IF_LINE], output logic [(8/NUM_AVST_IF_LINE)-1:0] ing_in_fpga_internal_pause_req[NUM_AVST_IF_LINE], input logic [DP_CHA_WIDTH-1:0] ing_in_cha[NUM_AVST_IF_LINE], input logic [TIMESTAMP_WIDTH-1:0] ing_in_timestamp_96b[NUM_AVST_IF_LINE], input logic ing_out_clk[NUM_AVST_IF_LINE], input logic ing_out_rst[NUM_AVST_IF_LINE], output logic ing_out_sop[NUM_AVST_IF_LINE], output logic ing_out_eop[NUM_AVST_IF_LINE], output logic ing_out_val[NUM_AVST_IF_LINE], input logic ing_out_rdy[NUM_AVST_IF_LINE], input logic [(8/NUM_AVST_IF_LINE)-1:0] ing_out_fpga_internal_pause_req[NUM_AVST_IF_LINE], output logic [(LOG2_DP_DATA_PATH1_WIDTH-3) -1:0] ing_out_mty[NUM_AVST_IF_LINE], output logic [2**LOG2_DP_DATA_PATH1_WIDTH - 1:0] ing_out_dat[NUM_AVST_IF_LINE], output logic [USR_ERROR_WIDTH-1:0] ing_out_err[NUM_AVST_IF_LINE], output logic [DP_CHA_WIDTH-1:0] ing_out_cha[NUM_AVST_IF_LINE], output logic [TIMESTAMP_WIDTH-1:0] ing_out_timestamp_96b[NUM_AVST_IF_LINE], input logic egr_in_clk[NUM_AVST_IF_FVL], input logic egr_in_rst[NUM_AVST_IF_FVL], input logic [USR_ERROR_WIDTH-1:0] egr_in_err[NUM_AVST_IF_FVL], input logic egr_in_val[NUM_AVST_IF_FVL], input logic egr_in_sop[NUM_AVST_IF_FVL], input logic egr_in_eop[NUM_AVST_IF_FVL], input logic [2**LOG2_DP_DATA_PATH1_WIDTH - 1:0] egr_in_dat[NUM_AVST_IF_FVL], input logic [DP_CHA_WIDTH-1:0] egr_in_cha[NUM_AVST_IF_FVL], // NB: not used currently input logic [(LOG2_DP_DATA_PATH1_WIDTH-3) -1:0] egr_in_mty[NUM_AVST_IF_FVL], output logic egr_in_rdy[NUM_AVST_IF_FVL], output logic [(8/NUM_AVST_IF_LINE)-1:0] egr_in_fpga_internal_pause_req[NUM_AVST_IF_LINE], input logic [TIMESTAMP_WIDTH-1:0] egr_in_timestamp_96b[NUM_AVST_IF_LINE], input logic egr_out_clk[NUM_AVST_IF_FVL], input logic egr_out_rst[NUM_AVST_IF_FVL], output logic egr_out_sop[NUM_AVST_IF_FVL], output logic egr_out_eop[NUM_AVST_IF_FVL], output logic egr_out_val[NUM_AVST_IF_FVL], input logic egr_out_rdy[NUM_AVST_IF_FVL], input logic [(8/NUM_AVST_IF_LINE)-1:0] egr_out_fpga_internal_pause_req[NUM_AVST_IF_LINE], output logic [DP_CHA_WIDTH-1:0] egr_out_cha[NUM_AVST_IF_FVL], output logic [(LOG2_DP_DATA_PATH0_WIDTH-3) -1:0] egr_out_mty[NUM_AVST_IF_FVL], output logic [2**LOG2_DP_DATA_PATH0_WIDTH - 1:0] egr_out_dat[NUM_AVST_IF_FVL], output logic [USR_ERROR_WIDTH-1:0] egr_out_err[NUM_AVST_IF_FVL], output logic [TIMESTAMP_WIDTH-1:0] egr_out_timestamp_96b[NUM_AVST_IF_LINE], `ifdef INCLUDE_DDR4 input wire ddr4a_avmm_0_clk, input wire ddr4a_avmm_0_reset_n, input wire ddr4a_avmm_0_waitrequest, input wire [255:0] ddr4a_avmm_0_readdata, input wire ddr4a_avmm_0_readdatavalid, output wire [6:0] ddr4a_avmm_0_burstcount, output wire [255:0] ddr4a_avmm_0_writedata, output wire [25:0] ddr4a_avmm_0_address, output wire ddr4a_avmm_0_write, output wire ddr4a_avmm_0_read, output wire [31:0] ddr4a_avmm_0_byteenable, input wire ddr4a_avmm_1_clk, input wire ddr4a_avmm_1_reset_n, input wire ddr4a_avmm_1_waitrequest, input wire [255:0] ddr4a_avmm_1_readdata, input wire ddr4a_avmm_1_readdatavalid, output wire [6:0] ddr4a_avmm_1_burstcount, output wire [255:0] ddr4a_avmm_1_writedata, output wire [25:0] ddr4a_avmm_1_address, output wire ddr4a_avmm_1_write, output wire ddr4a_avmm_1_read, output wire [31:0] ddr4a_avmm_1_byteenable, input wire ddr4b_avmm_0_clk, input wire ddr4b_avmm_0_reset_n, input wire ddr4b_avmm_0_waitrequest, input wire [255:0] ddr4b_avmm_0_readdata, input wire ddr4b_avmm_0_readdatavalid, output wire [6:0] ddr4b_avmm_0_burstcount, output wire [255:0] ddr4b_avmm_0_writedata, output wire [25:0] ddr4b_avmm_0_address, output wire ddr4b_avmm_0_write, output wire ddr4b_avmm_0_read, output wire [31:0] ddr4b_avmm_0_byteenable, input wire ddr4b_avmm_1_clk, input wire ddr4b_avmm_1_reset_n, input wire ddr4b_avmm_1_waitrequest, input wire [255:0] ddr4b_avmm_1_readdata, input wire ddr4b_avmm_1_readdatavalid, output wire [6:0] ddr4b_avmm_1_burstcount, output wire [255:0] ddr4b_avmm_1_writedata, output wire [25:0] ddr4b_avmm_1_address, output wire ddr4b_avmm_1_write, output wire ddr4b_avmm_1_read, output wire [31:0] ddr4b_avmm_1_byteenable, input wire ddr4c_avmm_clk, input wire ddr4c_avmm_reset_n, input wire ddr4c_avmm_waitrequest, input wire [127:0] ddr4c_avmm_readdata, input wire ddr4c_avmm_readdatavalid, output reg [6:0] ddr4c_avmm_burstcount, output reg [127:0] ddr4c_avmm_writedata, output reg [25:0] ddr4c_avmm_address, output reg ddr4c_avmm_write, output reg ddr4c_avmm_read, output reg [15:0] ddr4c_avmm_byteenable, input wire qdr_avmm_clk, input wire qdr_avmm_reset_n, input wire qdr_avmm_waitrequest [7:0], input wire [35:0] qdr_avmm_readdata [7:0], input wire qdr_avmm_readdatavalid [7:0], output reg [2:0] qdr_avmm_burstcount [7:0], output reg [35:0] qdr_avmm_writedata [7:0], output reg [21:0] qdr_avmm_address [7:0], output reg qdr_avmm_write [7:0], output reg qdr_avmm_read [7:0] `endif ); localparam SUB_AVMM_NUM = 2; localparam AFU_ID_L = LIGHTWEIGHT_MODE ? 64'h9FFA_8731_438C_4BA3 : 64'hC000_C966_0D82_4272; localparam AFU_ID_H = LIGHTWEIGHT_MODE ? 64'hADDF_01F4_E8B1_D90F : 64'h9AEF_FE5F_8457_0612; `default_nettype none localparam NUM_SUB_AFUS = 8; localparam NUM_PIPE_STAGES = 2; localparam C_SUB_AFUS_NOF_BITS = $clog2(NUM_SUB_AFUS); `ifdef INCLUDE_AFU_PCIE1 pcie1_plug pcie1_plug_inst ( .ffs_LP32ui_vl_sync_reset_n (pcie1_pcie_pins_perst_n), // synchronous to AVL clock .ffs_LP32ui_vl_sync_pwrgood_n (pcie1_pcie_pins_perst_n), // not synchronous to AVL clock // PCIe pins .pin_pcie_ref_clk_p (pcie1_pipe_gen3_x8_ref_clk), .pin_pcie_in_perst_n (pcie1_pcie_pins_perst_n), // connected to HIP .pin_pcie_rx_p (pcie1_pipe_gen3_x8_rx_serial), .pin_pcie_tx_p (pcie1_pipe_gen3_x8_tx_serial) ); `endif /* // ============================================================= // Register SR <--> PR signals at interface before consuming it // ============================================================= (* noprune *) logic [1:0] pck_cp2af_pwrState_T1; (* noprune *) logic pck_cp2af_error_T1; logic pck_cp2af_softReset_T1; t_if_ccip_Rx pck_cp2af_sRx_T1; t_if_ccip_Tx pck_af2cp_sTx_T0; // ============================================================= // Register PR <--> PR signals near interface before consuming it // ============================================================= ccip_interface_reg inst_green_ccip_interface_reg ( .pClk (pClk), .pck_cp2af_softReset_T0 (pck_cp2af_softReset), .pck_cp2af_pwrState_T0 (pck_cp2af_pwrState), .pck_cp2af_error_T0 (pck_cp2af_error), .pck_cp2af_sRx_T0 (pck_cp2af_sRx), .pck_af2cp_sTx_T0 (pck_af2cp_sTx_T0), .pck_cp2af_softReset_T1 (pck_cp2af_softReset_T1), .pck_cp2af_pwrState_T1 (pck_cp2af_pwrState_T1), .pck_cp2af_error_T1 (pck_cp2af_error_T1), .pck_cp2af_sRx_T1 (pck_cp2af_sRx_T1), .pck_af2cp_sTx_T1 (pck_af2cp_sTx) ); */ //split c0rx into host and mmio wire afu_clk; assign afu_clk = pClk ; t_if_ccip_Rx pck_cp2af_mmio_sRx; t_if_ccip_Rx pck_cp2af_host_sRx; always_comb begin pck_cp2af_mmio_sRx = pck_cp2af_sRx; pck_cp2af_host_sRx = pck_cp2af_sRx; //disable rsp valid on mmio path pck_cp2af_mmio_sRx.c0.rspValid = 0; //disable mmio valid on host path pck_cp2af_host_sRx.c0.mmioRdValid = 0; pck_cp2af_host_sRx.c0.mmioWrValid = 0; end // ==================================================================== // // Instantiate a memory properties factory (MPF) between the external // interface and the AFU, adding support for virtual memory and // control over memory ordering. // // ==================================================================== // // The AFU exposes the primary AFU device feature header (DFH) at MMIO // address 0. MPF defines a set of its own DFHs. The AFU must // build its feature chain to point to the MPF chain. The AFU must // also tell the MPF module the MMIO address at which MPF should start // its feature chain. // //Note: with ENABLE_SEPARATE_MMIO_FIFO, MPF will not receive or forward //any mmio requests localparam MPF_DFH_MMIO_ADDR = 'h0000; localparam MPF_DFH_MMIO_NEXT_ADDR = 'h0000; // // MPF represents CCI as a SystemVerilog interface, derived from the // same basic types defined in ccip_if_pkg. Interfaces reduce the // number of internal MPF module parameters, since each internal MPF // shim has a bus connected toward the AFU and a bus connected toward // the FIU. // // // Expose FIU as an MPF interface // cci_mpf_if fiu(.clk(afu_clk)); // The CCI wires to MPF mapping connections have identical naming to // the standard AFU. The module exports an interface named "fiu". ccip_wires_to_mpf #( // All inputs and outputs in PR region (AFU) must be registered! .REGISTER_INPUTS(1), .REGISTER_OUTPUTS(1) ) map_ifc ( .pClk(afu_clk), .pck_cp2af_softReset(pck_cp2af_softReset), .pck_cp2af_sRx(pck_cp2af_host_sRx), .pck_af2cp_sTx(pck_af2cp_sTx), .* ); // // Instantiate MPF with the desired properties. // cci_mpf_if afu(.clk(afu_clk)); cci_mpf #( // Should read responses be returned in the same order that // the reads were requested? .SORT_READ_RESPONSES(1), // Should the Mdata from write requests be returned in write // responses? If the AFU is simply counting write responses // and isn't consuming Mdata, then setting this to 0 eliminates // the memory and logic inside MPF for preserving Mdata. .PRESERVE_WRITE_MDATA(0), // Enable virtual to physical translation? When enabled, MPF // accepts requests with either virtual or physical addresses. // Virtual addresses are indicated by setting the // addrIsVirtual flag in the MPF extended Tx channel // request header. .ENABLE_VTP(0), // Enable mapping of eVC_VA to physical channels? AFUs that both use // eVC_VA and read back memory locations written by the AFU must either // emit WrFence on VA or use explicit physical channels and enforce // write/read order. Each method has tradeoffs. WrFence VA is expensive // and should be emitted only infrequently. Memory requests to eVC_VA // may have higher bandwidth than explicit mapping. The MPF module for // physical channel mapping is optimized for each CCI platform. // // If you set ENFORCE_WR_ORDER below you probably also want to set // ENABLE_VC_MAP. // // The mapVAtoPhysChannel extended header bit must be set on each // request to enable mapping. .ENABLE_VC_MAP(0), // When ENABLE_VC_MAP is set the mapping is either static for the entire // run or dynamic, changing in response to traffic patterns. The mapper // guarantees synchronization when the mapping changes by emitting a // WrFence on eVC_VA and draining all reads. Ignored when ENABLE_VC_MAP // is 0. .ENABLE_DYNAMIC_VC_MAPPING(0), // Should write/write and write/read ordering within a cache // be enforced? By default CCI makes no guarantees on the order // in which operations to the same cache line return. Setting // this to 1 adds logic to filter reads and writes to ensure // that writes retire in order and the reads correspond to the // most recent write. // // *** Even when set to 1, MPF guarantees order only within // *** a given virtual channel. There is no guarantee of // *** order across virtual channels and no guarantee when // *** using eVC_VA, since it spreads requests across all // *** channels. Synchronizing writes across virtual channels // *** can be accomplished only by requesting a write fence on // *** eVC_VA. Syncronizing writes across virtual channels // *** and then reading back the same data requires both // *** requesting a write fence on eVC_VA and waiting for the // *** corresponding write fence response. // .ENFORCE_WR_ORDER(0), // Enable partial write emulation. CCI has no support for masked // writes that merge new data with existing data in a line. MPF // adds byte-level masks to the write request header and emulates // partial writes as a read-modify-write operation. When coupled // with ENFORCE_WR_ORDER, partial writes are free of races on the // FPGA side. There are no guarantees of atomicity and there is // no protection against races with CPU-generates writes. .ENABLE_PARTIAL_WRITES(0), // Address of the MPF feature header. See comment above. .DFH_MMIO_BASE_ADDR(MPF_DFH_MMIO_ADDR), .DFH_MMIO_NEXT_ADDR(MPF_DFH_MMIO_NEXT_ADDR) ) mpf ( .clk(afu_clk), .fiu, .afu, .c0NotEmpty(), .c1NotEmpty() ); // ==================================================================== // // Now CCI is exposed as an MPF interface through the object named // "afu". Two primary strategies are available for connecting // a design to the interface: // // (1) Use the MPF-provided constructor functions to generate // CCI request structures and pass them directly to MPF. // See, for example, cci_mpf_defaultReqHdrParams() and // cci_c0_genReqHdr() in cci_mpf_if_pkg.sv. // // (1) Map "afu" back to standard CCI wires. This is the strategy // used below to map an existing AFU to MPF. // // ==================================================================== // // Convert MPF interfaces back to the standard CCI structures. // t_if_ccip_Rx mpf2af_sRxPort; t_if_ccip_Tx af2mpf_sTxPort; // // The cci_mpf module has already registered the Rx wires heading // toward the AFU, so wires are acceptable. // always_comb begin mpf2af_sRxPort.c0 = afu.c0Rx; mpf2af_sRxPort.c1 = afu.c1Rx; mpf2af_sRxPort.c0TxAlmFull = afu.c0TxAlmFull; mpf2af_sRxPort.c1TxAlmFull = afu.c1TxAlmFull; afu.c0Tx = cci_mpf_cvtC0TxFromBase(af2mpf_sTxPort.c0); if (cci_mpf_c0TxIsReadReq(afu.c0Tx)) begin // Treat all addresses as virtual. afu.c0Tx.hdr.ext.addrIsVirtual = 1'b0; // Enable eVC_VA to physical channel mapping. This will only // be triggered when ENABLE_VC_MAP is set above. afu.c0Tx.hdr.ext.mapVAtoPhysChannel = 1'b0; // Enforce load/store and store/store ordering within lines. // This will only be triggered when ENFORCE_WR_ORDER is set. afu.c0Tx.hdr.ext.checkLoadStoreOrder = 1'b0; end afu.c1Tx = cci_mpf_cvtC1TxFromBase(af2mpf_sTxPort.c1); if (cci_mpf_c1TxIsWriteReq(afu.c1Tx)) begin // Treat all addresses as virtual. afu.c1Tx.hdr.ext.addrIsVirtual = 1'b0; // Enable eVC_VA to physical channel mapping. This will only // be triggered when ENABLE_VC_MAP is set above. afu.c1Tx.hdr.ext.mapVAtoPhysChannel = 1'b0; // Enforce load/store and store/store ordering within lines. // This will only be triggered when ENFORCE_WR_ORDER is set. afu.c1Tx.hdr.ext.checkLoadStoreOrder = 1'b0; end afu.c2Tx = af2mpf_sTxPort.c2; end //=============================================================================================== // User AFU goes here //=============================================================================================== afu afu_inst( .afu_clk(afu_clk), .reset ( fiu.reset ) , .cp2af_sRxPort ( mpf2af_sRxPort ) , .cp2af_mmio_c0rx ( pck_cp2af_mmio_sRx.c0 ) , .af2cp_sTxPort ( af2mpf_sTxPort ) ); //######################################################################// //######################################################################// //######################################################################// //######################################################################// //######################################################################// // // USER LOGIC - ADD/REMOVE/MODIFY your logic below // endmodule - Copy attached afu.qsf file into the design.
- Compile design using make flow. Note: You need to set items to remove diagnostics and external memories.
$ make 2x2x25G GUI=1 INCLUDE_DIAGNOSTICS=0 INCLUDE_MEMORY=0 \ PAC_VER_MAJOR=3 PAC_VER_MINOR=5 PAC_VER_PATCH=6 \ REVISION_ID=12345678 INCLUDE_AFU_PCIE1=0 AFU_ROOT=<absolute path>/hw/hls_afu/hwNote: The compile process takes approximately 1.5 hours.