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1. About the High Bandwidth Memory (HBM2) Interface Intel® FPGA IP
2. Introduction to High Bandwidth Memory
3. Stratix® 10 HBM2 Architecture
4. Creating and Parameterizing the High Bandwidth Memory (HBM2) Interface Intel® FPGA IP
5. Simulating the High Bandwidth Memory (HBM2) Interface Intel® FPGA IP
6. High Bandwidth Memory (HBM2) Interface Intel® FPGA IP Interface
7. High Bandwidth Memory (HBM2) Interface Intel® FPGA IP Controller Performance
8. High Bandwidth Memory (HBM2) Interface Intel® FPGA IP User Guide Archives
9. Document Revision History for High Bandwidth Memory (HBM2) Interface FPGA IP User Guide
4.2.1. General Parameters for High Bandwidth Memory (HBM2) Interface Intel® FPGA IP
4.2.2. FPGA I/O Parameters for High Bandwidth Memory (HBM2) Interface Intel® FPGA IP
4.2.3. Controller Parameters for High Bandwidth Memory (HBM2) Interface Intel® FPGA IP
4.2.4. Diagnostic Parameters for High Bandwidth Memory (HBM2) Interface Intel® FPGA IP
4.2.5. Example Designs Parameters for High Bandwidth Memory (HBM2) Interface Intel® FPGA IP
4.2.6. Register Map IP-XACT Support for HBM2 IP
5.1. High Bandwidth Memory (HBM2) Interface Intel® FPGA IP Example Design
5.2. Simulating High Bandwidth Memory (HBM2) Interface Intel® FPGA IP with ModelSim* and Questa*
5.3. Simulating High Bandwidth Memory (HBM2) Interface Intel® FPGA IP with Synopsys VCS*
5.4. Simulating High Bandwidth Memory (HBM2) Interface Intel® FPGA IP with Riviera-PRO*
5.5. Simulating High Bandwidth Memory (HBM2) Interface Intel® FPGA IP with Cadence Xcelium* Parallel Simulator
5.6. Simulating High Bandwidth Memory (HBM2) Interface Intel® FPGA IP for High Efficiency
5.7. Simulating High Bandwidth Memory (HBM2) Interface IP Instantiated in Your Project
6.1. High Bandwidth Memory (HBM2) Interface Intel® FPGA IP High Level Block Diagram
6.2. High Bandwidth Memory (HBM2) Interface Intel® FPGA IP Controller Interface Signals
6.3. User AXI Interface Timing
6.4. User APB Interface Timing
6.5. User-controlled Accesses to the HBM2 Controller
6.6. Soft AXI Switch
7.1. High Bandwidth Memory (HBM2) DRAM Bandwidth
7.2. High Bandwidth Memory (HBM2) Interface Intel® FPGA IP HBM2 IP Efficiency
7.3. High Bandwidth Memory (HBM2) Interface Intel® FPGA IP Latency
7.4. High Bandwidth Memory (HBM2) Interface Intel® FPGA IP Timing
7.5. High Bandwidth Memory (HBM2) Interface Intel® FPGA IP DRAM Temperature Readout
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6.5.6.1. Interrupt Enable and Conditions for Interrupt Generation
If you want interrupts to occur based on certain conditions, you must set the conditions to enable interrupt generation.
To enable interrupt generation, issue a Write command to address location 16’h0100 (for Pseudo Channel 0) and 16’h0200 (for Pseudo Channel 1), with the corresponding Write Data (PWDATA).
- PWDATA[0] – Interrupt enable.
- PWDATA[11:1] - Lists the various status signals that you can use, alone or in combination, to trigger the Interrupt signal.
- Set the Mask value to 1’b0 to use the corresponding error condition to generate the Interrupt signal.
- If you set the Mask value to 1’b1, the Interrupt generator ignores that specific error condition. For example, to use the double-bit error condition to generate the Interrupt signal, set PWDATA[2] to 1’b0.
The following table describes the 16-bit Write Data (PWDATA) for setting the Interrupt Enable, and the conditions of the interrupt.
Write Data Bit Definition | Description |
---|---|
[0] | Interrupt Enable: Enables interrupt to the HBM2 controller when the conditions set in PWDATA[11:1] are TRUE. 1 – Enable Interrupt 0 – Disable Interrupt |
[1] | SBE Interrupt Mask. |
[2] | DBE Interrupt Mask. |
[3] | Read DPE Interrupt Mask. |
[4] | Write DPE Interrupt Mask. |
[5] | Address Command Interrupt Mask. |
[6] | CATTRIP Interrupt Mask. |
[7] | Calibration Interrupt Mask. |
[8] | Write SRAM SBE Interrupt Mask. |
[9] | Write SRAM DBE Interrupt Mask. |
[10] | Read SRAM SBE Interrupt Mask. |
[11] | Read SRAM DBE Interrupt Mask. |
[15:12] | Reserved. |