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1.1. Features
1.2. Hardware and Software Requirements
1.3. Functional Description
1.4. Hardware Testing
1.5. TCL Script
1.6. Interface Signals
1.7. Configuration Registers and Status Registers
1.8. Regenerating Triple-Speed Ethernet Intel® FPGA IP
1.9. Document Revision History for AN 830: Intel® FPGA Triple-Speed Ethernet and On-Board PHY Chip Reference Design for Intel® Stratix® 10 Devices
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1.3.3. Reset Scheme
Figure 3. Reset Scheme