2021.05.19 |
- Updated the steps in the following topics:
- Test Case—Internal MAC Loopback
- Test Case— Avalon® Streaming Reverse Loopback
- Updated the software requirement in Hardware and Software Requirements.
- Made editorial edits throughout the document.
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2020.10.14 |
- Updated Table: Ethernet Packet Generator Configuration Registers Map to remove rand_seed2.
- Updated Table: Ethernet Packet Monitor Configuration Registers Map to update the names and descriptions for the following registers:
- byte_rx_count
- cycle_rx_count
- Made minor editorial edits throughout the document.
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2019.10.18 |
- Updated the development kit name from Intel® Stratix® 10 GX Signal Integrity (SI) development kit to Intel® Stratix® 10 GX FPGA development kit.
- Added a new topic—Regenerating Triple-Speed Ethernet Intel® FPGA IP .
- Updated the Intel® FPGA Triple-Speed Ethernet and On-Board PHY Chip Reference Design for Intel® Stratix® 10 Devices topic.
- Updated the Hardware and Software Requirements topic.
- Updated the Test Case—Internal MAC Loopback topic:
- Updated the steps to run the hardware test case.
- Updated Figures:
- Sample Output—MAC Configuration Summary
- Sample Output—PCS Configuration Summary
- Sample Output—On-Board PHY Chip Configuration Summary
- Updated the Test Case— Avalon® -ST Reverse Loopback topic:
- Updated the steps to run the hardware test case.
- Updated Figures:
- Sample Output—MAC Configuration Summary
- Sample Output—PCS Configuration Summary
- Sample Output—On-Board PHY Chip Configuration Summary
- Sample Output—TX and RX MAC Statistic Counters
- Updated Table: Design Components to update the descriptions for the following components:
- Triple-Speed Ethernet IP core
- I/O Phase-Locked Loop (PLL) core
- Updated Figures:
- Block Diagram
- Clocking Scheme
- Reset Scheme
- Removed Figure: Configuration of U5 OUT8 Frequency in Clock Controller.
- Updated for latest Intel® branding standards.
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2019.04.18 |
- Updated Figure: Block Diagram.
- Updated for latest Intel® branding standards.
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