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1.1. Features
1.2. Hardware and Software Requirements
1.3. Functional Description
1.4. Hardware Testing
1.5. TCL Script
1.6. Interface Signals
1.7. Configuration Registers and Status Registers
1.8. Regenerating Triple-Speed Ethernet Intel® FPGA IP
1.9. Document Revision History for AN 830: Intel® FPGA Triple-Speed Ethernet and On-Board PHY Chip Reference Design for Intel® Stratix® 10 Devices
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1.6. Interface Signals
Signal | Direction | Width | Description |
---|---|---|---|
clk_clk | Input | 1 | This is the reference design clock, which derived from the IOPLL Intel® FPGA IP. |
reset_reset | Input | 1 | A single reset signal that used to reset all logic in the reference design. This reset signal is connected to a push button (USER_PB0). |
triple_speed_ethernet_0_pcs_ ref_clk_clock_connection_clk | Input | 1 | The 125 MHz reference clock for the 1.25 Gbps serial LVDS I/O interface. This clock is sourced from a dedicated reference clock source, which is in the same IO bank as triple_speed_ethernet_0_ serial_connection_txp_0 and triple_speed_ethernet_0_ serial_connection_rxp_0 pins. |
Signal | Direction | Width | Description |
---|---|---|---|
triple_speed_ethernet_0_ serial_connection_txp_0 | Output | 1 | SGMII serial differential transmit interface. Connect this interface to the on-board PHY chip. |
triple_speed_ethernet_0_ serial_connection_rxp_0 | Input | 1 | SGMII serial differential receive interface. Connect this interface to the on-board PHY chip. |
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