Triple-Speed Ethernet Intel® FPGA IP |
- This IP provides an integrated Ethernet MAC, PCS, and PMA solution for Ethernet applications.
- During data transmission, the Triple-Speed Ethernet Intel® FPGA IP transmits Ethernet packets from Avalon® streaming interface to a 1.25-Gbps serial LVDS I/O interface and the Ethernet packets receiving operation is done with the opposite way.
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Ethernet Packet Generator |
- This module is a Platform Designer custom component that generates Ethernet packets.
- It consists of sub-components such as Ethernet packet generation block, CRC generator, Avalon® memory-mapped registers, and shift register.
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Ethernet Packet Monitor |
- This module is a Platform Designer custom component that verifies the payload of all received packets and collects the statistics of each received packet such as number of bytes received.
- It consists of sub-components such as CRC checker and Avalon® memory-mapped registers.
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Error Adapter |
- This adapter is a Platform Designer custom component that used to connect mismatched Avalon® streaming source and sink interface.
- By using this adapter, data source and data sink with different bit width can be connected together. For RX-to-TX Avalon® streaming reverse loopback in this reference design, ff_tx_err is a 1-bit error signal while rx_err is a 6-bit error signal.
- This adapter can match the error conditions that are handled by the Avalon® streaming source and Avalon® streaming sink.
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Avalon® Streaming Multiplexer |
- This multiplexer is a Platform Designer custom component that accepts data on its two Avalon® streaming sink interfaces and multiplexes the data for transmission on its Avalon® streaming source interface.
- One of the Avalon® streaming sink interface is connected to the Avalon® streaming source interface of Ethernet Packet Generator (For forward MAC loopback) and another Avalon® streaming sink interface is connected to the Avalon® streaming source interface of Error Adapter (for reverse loopback).
- The packets on Avalon® streaming source interface of this multiplexer will be transmitted to Triple-Speed Ethernet Intel® FPGA IP.
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Avalon® Streaming Splitter |
- This splitter is a Platform Designer custom component that accepts data from Triple-Speed Ethernet Intel® FPGA IP through Avalon® streaming sink interface and splits the data on its two Avalon® streaming source interfaces.
- One of its Avalon® Streaming source interface is connected to the Avalon® streaming sink interface of Ethernet Packet Monitor (for forward MAC loopback) and another Avalon® streaming source interface is connected to the Avalon® streaming sink interface of Error Adapter (for reverse loopback).
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JTAG to Avalon® Master Bridge Intel® FPGA IP |
This IP provides a connection between System Console and Platform Designer system through the physical interface. The System Console initiates Avalon® memory-mapped transactions by sending encoded streams of bytes through bridge’s physical interface. |
IOPLL Intel® FPGA IP |
- This IP generates a 100 MHz PLL output clock (clk_100M).
- This output clock is the clock source for Platform Designer system. All components in this reference design use this output clock.
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