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1.1. Features
1.2. Hardware and Software Requirements
1.3. Functional Description
1.4. Hardware Testing
1.5. TCL Script
1.6. Interface Signals
1.7. Configuration Registers and Status Registers
1.8. Regenerating Triple-Speed Ethernet Intel® FPGA IP
1.9. Document Revision History for AN 830: Intel® FPGA Triple-Speed Ethernet and On-Board PHY Chip Reference Design for Intel® Stratix® 10 Devices
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1.5.2. Ethernet Packet Generator Script
The Ethernet Packet Generator script, eth_gen_start.tcl contains the parameters and settings to configure the Ethernet Packet Generator registers in this reference design.
Parameter | Description |
---|---|
number_packet | Sets the total number of packets to be generated by the packet generator. |
eth_gen | Enables or disables the packet generator. |
length_sel | Selects fixed or random packet length. |
pkt_length | Sets the fixed packet length. The packet length can be a value between 24 to 9600 bytes. |
pattern_sel | Selects the data pattern for the random packet length. |
rand_seed | Sets the initial random seed for the PRBS generator. This parameter is only valid when you select random packet length. |
source_addr | Sets the source MAC address. |
destination_addr | Sets the destination MAC address. |