AN 750: Using the Altera PDN Tool to Optimize Your Power Delivery Network Design

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ID 683155
Date 7/08/2015
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Document Table of Contents
Document Table of Contents x
1. AN 750: Using the Altera PDN Tool to Optimize Your Power Delivery Network Design
1. AN 750: Using the Altera PDN Tool to Optimize Your Power Delivery Network Design x
1.1. Impact of a Poor PDN 1.2. PDN Circuit Topology 1.3. Estimating the Current Requirements of your FPGA Design 1.4. Calculating Ztarget 1.5. Example Design 1.6. PDN Design Optimization Study 1.7. Document Revision History
1.3. Estimating the Current Requirements of your FPGA Design x
1.3.1. FPGA Functional Blocks 1.3.2. Clock Frequencies 1.3.3. GPIO 1.3.4. Transceivers 1.3.5. Data Patterns
1.6. PDN Design Optimization Study x
1.6.1. Initial Stackup Entry 1.6.2. Using the Correct Number of Power/Ground Via Pairs 1.6.3. Using the Correct Number of Power/Ground Via Pairs and Layer Number 1.6.4. Corrected Number of Power/Ground Via Pairs and Layer Numbers 1.6.5. Moving Supplies to Optimal Layers 1.6.6. Moving Power and Ground Planes Closer Together 1.6.7. Move Decoupling Capacitors to the Top Surface of the PCB 1.6.8. Using X2Y Decoupling Capacitors 1.6.9. Using Ultra–Low ESR Bulk Capacitors 1.6.10. Swapping VCC on Layer 9 with VCC, VCCT_GXB, and VCCR_GXB on Layer 4 1.6.11. Assessing How Much Total Capacitance Might be Required 1.6.12. Using the Core Clock Frequency and Current Ramp Up Period Parameters 1.6.13. Overall Design Study Capacitor Savings 1.6.14. Overall Summary 1.6.15. References
1. AN 750: Using the Altera PDN Tool to Optimize Your Power Delivery Network Design

1.6.9. Using Ultra–Low ESR Bulk Capacitors

Significant improvements were made using low ESL X2Y capacitors instead of standard packaged capacitors. Some improvements can be made at low frequencies by using ultra-low Effective Series Resistance (ESR) bulk capacitors. Ultra-low ESR bulk capacitors can have very low resistances of 5mR when compared with approximately 50mR for standard bulk capacitors. You can use Ultra-low ESR bulk capacitors to reduce the number of bulk capacitors required for meeting Ztarget at low frequencies.

Enter parameters of your own user capacitors in the Library tab of the PDN Tool. In this example, 680uF and 1000uF Panasonic POSCAP Tantalum-Polymer Capacitors with an ESR of 0.005 were used. 0.005 is entered for User5 and User6 of the Bulk Cap ESR(R) column. On the System Decap tab 680 and 1000 is entered for User5 and User6. In this case the higher 680uF and 1000uF may also help to reduce the total capacitor count. The PDN Tool reports that using ultra-low ESR capacitors reduces bulk capacitor count of the VCC, VCCT_GXB, and VCCR_GXB supplies as shown below.

Figure 26. Capacitors Required for the VCC, VCCT_GXB, and VCCR_GXB Supplies when Ultra-Low ESR Bulk Capacitors

The VCCT_GXB, and VCCR_GXB supplies now require 25 and 22 capacitors respectively. VCC bulk capacitors are reduced from 23 to 17 when using ultra-low ESR bulk capacitors. However the target impedance is still not met at high frequencies.

The PCB, stackup, layer allocation and capacitor use and placement are now highly optimized. Further evaluation of the supply rail layers can still be done. The VCC supply is placed on Layer 9, but VCCT_GXB, and VCCR_GXB are placed on Layer 4. Layer 4 is more optimal because it has less vertical inductance.

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