AN 750: Using the Altera PDN Tool to Optimize Your Power Delivery Network Design

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ID 683155
Date 7/08/2015
Public
Document Table of Contents
Document Table of Contents x
1. AN 750: Using the Altera PDN Tool to Optimize Your Power Delivery Network Design
1. AN 750: Using the Altera PDN Tool to Optimize Your Power Delivery Network Design x
1.1. Impact of a Poor PDN 1.2. PDN Circuit Topology 1.3. Estimating the Current Requirements of your FPGA Design 1.4. Calculating Ztarget 1.5. Example Design 1.6. PDN Design Optimization Study 1.7. Document Revision History
1.3. Estimating the Current Requirements of your FPGA Design x
1.3.1. FPGA Functional Blocks 1.3.2. Clock Frequencies 1.3.3. GPIO 1.3.4. Transceivers 1.3.5. Data Patterns
1.6. PDN Design Optimization Study x
1.6.1. Initial Stackup Entry 1.6.2. Using the Correct Number of Power/Ground Via Pairs 1.6.3. Using the Correct Number of Power/Ground Via Pairs and Layer Number 1.6.4. Corrected Number of Power/Ground Via Pairs and Layer Numbers 1.6.5. Moving Supplies to Optimal Layers 1.6.6. Moving Power and Ground Planes Closer Together 1.6.7. Move Decoupling Capacitors to the Top Surface of the PCB 1.6.8. Using X2Y Decoupling Capacitors 1.6.9. Using Ultra–Low ESR Bulk Capacitors 1.6.10. Swapping VCC on Layer 9 with VCC, VCCT_GXB, and VCCR_GXB on Layer 4 1.6.11. Assessing How Much Total Capacitance Might be Required 1.6.12. Using the Core Clock Frequency and Current Ramp Up Period Parameters 1.6.13. Overall Design Study Capacitor Savings 1.6.14. Overall Summary 1.6.15. References
1. AN 750: Using the Altera PDN Tool to Optimize Your Power Delivery Network Design

1.3.4. Transceivers

Power requirements increase with frequency so when using transceivers that can be reconfigured between multiple data rates, you should ensure that you use your highest datarate for your power estimations. The estimates should use the correct, worst case Physical Coding Sub-layers (PCSs) for your design.

Depending on protocol and datarate, transceivers use the following PCSs:
  • PCI Express Hard-IP
  • Enhanced PCS
  • Standard PCS

When implementing dynamic reconfiguration to switch between the Standard and Enhanced PCS, Altera recommends using the PPPA to determine whether the Standard or Enhanced PCS consumes more power for your design.

As an example, dynamic reconfiguration is used to switch between Altera IP 1G/10G Ethernet IP using the Standard PCS for 1Gbs Ethernet and the Enhanced PCS for 10Gbps Ethernet. To determine worst case power estimations, use the 10Gbs Ethernet using the Enhanced PCS.

If you intend to use Decision Feedback Equalization (DFE) or Adaptive Equalization (AEQ) with your transceivers you should include these in your power estimations. Adding DFE and AEQ adaption to your design increases the transceiver power requirements and the PDN design challenges. The estimations should be based on channels that use DFE and AEQ. If you do not use DFE and AEQ for some channels, then do not not include them in your power estimations.

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