AN 750: Using the Altera PDN Tool to Optimize Your Power Delivery Network Design

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ID 683155
Date 7/08/2015
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Document Table of Contents
Document Table of Contents x
1. AN 750: Using the Altera PDN Tool to Optimize Your Power Delivery Network Design
1. AN 750: Using the Altera PDN Tool to Optimize Your Power Delivery Network Design x
1.1. Impact of a Poor PDN 1.2. PDN Circuit Topology 1.3. Estimating the Current Requirements of your FPGA Design 1.4. Calculating Ztarget 1.5. Example Design 1.6. PDN Design Optimization Study 1.7. Document Revision History
1.3. Estimating the Current Requirements of your FPGA Design x
1.3.1. FPGA Functional Blocks 1.3.2. Clock Frequencies 1.3.3. GPIO 1.3.4. Transceivers 1.3.5. Data Patterns
1.6. PDN Design Optimization Study x
1.6.1. Initial Stackup Entry 1.6.2. Using the Correct Number of Power/Ground Via Pairs 1.6.3. Using the Correct Number of Power/Ground Via Pairs and Layer Number 1.6.4. Corrected Number of Power/Ground Via Pairs and Layer Numbers 1.6.5. Moving Supplies to Optimal Layers 1.6.6. Moving Power and Ground Planes Closer Together 1.6.7. Move Decoupling Capacitors to the Top Surface of the PCB 1.6.8. Using X2Y Decoupling Capacitors 1.6.9. Using Ultra–Low ESR Bulk Capacitors 1.6.10. Swapping VCC on Layer 9 with VCC, VCCT_GXB, and VCCR_GXB on Layer 4 1.6.11. Assessing How Much Total Capacitance Might be Required 1.6.12. Using the Core Clock Frequency and Current Ramp Up Period Parameters 1.6.13. Overall Design Study Capacitor Savings 1.6.14. Overall Summary 1.6.15. References
1. AN 750: Using the Altera PDN Tool to Optimize Your Power Delivery Network Design

1.4. Calculating Ztarget

A PDN should have a low enough target impedance (Ztarget) to meet the voltage ripple requirements under maximum dynamic current requirements.

Figure 2. Ztarget Formula

This formula shows:

  • A decrease in voltage rail decreases Ztarget
  • A decrease in allowed voltage ripple decreases Ztarget
  • An increase in dynamic current decreases Ztarget

Very low target impedances require significant effort to design a sufficient PDN.

It can be challenging to provide PCB decoupling for the FPGA core (VCC), and transceiver VCCR_GXB, VCCT_GXB supplies. The low voltage, high current, VCC supply results in low target impedance. The transceiver VCCR_GXB and VCCT_GXB supplies have lower current than the VCC supply, but have low ripple requirements and hence low target impedance.

Assuming the following requirements, Ztarget can be calculated for the following VCC, VCCR_GXB, and VCCT_GXB cases. The current transient %, and allowable ripple % recommendations can be found on the Introduction tab of the PDN tool.

Table 1.   Ztarget Calculations for VCC, VCCR_GXB, and VCCT_GXB Supplies

Supply Name

Nominal Voltage (V)

Allowable Ripple (%)

Imax (A)

Current Transient (%)

Target Impedance (mR)

VCC

0.9

5

30

50

3

VCCR_GXB

1.0

3

6

30

16.67

VCCT_GXB

1.0

2

2

50

20

Additional challenges may occur when sharing supply rails with differing current requirements such as VCCR_GXB and VCCT_GXB. The worst case combination of higher IMax of the VCCR_GXB supply and lower ripple and high current transient of the VCCT_GXB supply, can create very low target impedances. Using the x or x/related options in the PDN Tool helps reduce the decoupling burden by estimating synchronous versus non-synchronous current switching.

In this application note, the VCCR_GXB and VCCT_GXB supplies are considered separately because it results in decoupling solutions with fewer PCB decoupling capacitors.

This application note focuses on the FPGA VCC, VCCT_GXB, and VCCR_GXB supplies that have low target impedance and require additional effort to decouple. Altera recommends that you analyze the performance of all design supplies.

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