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1.6.1. Initial Stackup Entry
1.6.2. Using the Correct Number of Power/Ground Via Pairs
1.6.3. Using the Correct Number of Power/Ground Via Pairs and Layer Number
1.6.4. Corrected Number of Power/Ground Via Pairs and Layer Numbers
1.6.5. Moving Supplies to Optimal Layers
1.6.6. Moving Power and Ground Planes Closer Together
1.6.7. Move Decoupling Capacitors to the Top Surface of the PCB
1.6.8. Using X2Y Decoupling Capacitors
1.6.9. Using Ultra–Low ESR Bulk Capacitors
1.6.10. Swapping VCC on Layer 9 with VCC, VCCT_GXB, and VCCR_GXB on Layer 4
1.6.11. Assessing How Much Total Capacitance Might be Required
1.6.12. Using the Core Clock Frequency and Current Ramp Up Period Parameters
1.6.13. Overall Design Study Capacitor Savings
1.6.14. Overall Summary
1.6.15. References
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1.7. Document Revision History
Chapter | Document Version | Changes Made |
---|---|---|
Example Design | 2015.07.08 | Updated the "Power Group Configuration and Current Entry for the Example Design" figure. |
PDN Design Optimization Study | 2015.07.08 | Added a comment about "Feffective increasing with efficiency". |
Date | Document Version | Changes Made |
---|---|---|
July 2015 | 2015.07.02 | Initial release. |