AN 750: Using the Altera PDN Tool to Optimize Your Power Delivery Network Design

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ID 683155
Date 7/08/2015
Public
Document Table of Contents
Document Table of Contents x
1. AN 750: Using the Altera PDN Tool to Optimize Your Power Delivery Network Design
1. AN 750: Using the Altera PDN Tool to Optimize Your Power Delivery Network Design x
1.1. Impact of a Poor PDN 1.2. PDN Circuit Topology 1.3. Estimating the Current Requirements of your FPGA Design 1.4. Calculating Ztarget 1.5. Example Design 1.6. PDN Design Optimization Study 1.7. Document Revision History
1.3. Estimating the Current Requirements of your FPGA Design x
1.3.1. FPGA Functional Blocks 1.3.2. Clock Frequencies 1.3.3. GPIO 1.3.4. Transceivers 1.3.5. Data Patterns
1.6. PDN Design Optimization Study x
1.6.1. Initial Stackup Entry 1.6.2. Using the Correct Number of Power/Ground Via Pairs 1.6.3. Using the Correct Number of Power/Ground Via Pairs and Layer Number 1.6.4. Corrected Number of Power/Ground Via Pairs and Layer Numbers 1.6.5. Moving Supplies to Optimal Layers 1.6.6. Moving Power and Ground Planes Closer Together 1.6.7. Move Decoupling Capacitors to the Top Surface of the PCB 1.6.8. Using X2Y Decoupling Capacitors 1.6.9. Using Ultra–Low ESR Bulk Capacitors 1.6.10. Swapping VCC on Layer 9 with VCC, VCCT_GXB, and VCCR_GXB on Layer 4 1.6.11. Assessing How Much Total Capacitance Might be Required 1.6.12. Using the Core Clock Frequency and Current Ramp Up Period Parameters 1.6.13. Overall Design Study Capacitor Savings 1.6.14. Overall Summary 1.6.15. References
1. AN 750: Using the Altera PDN Tool to Optimize Your Power Delivery Network Design

1.1. Impact of a Poor PDN

A stable power supply is the foundation of your FPGA design. It helps ensure that the device is within electrical specifications. A robust Power Delivery Network (PDN) that manages voltage ripple, is an important part of your power supply design.

With an increase in current loading, an insufficient PDN can result in excessive voltage ripple, voltage drops, and VRM instability. Voltage ripple on VCC supplies can cause brown-out conditions or timing margin reduction through power supply noise induced jitter. This can lead to data integrity problems.

A robust PDN is important for transceiver designs. A transceivers performance can be adversely affected by voltage ripple on its power supplies. Increased voltage ripple on transceiver power supplies can increase the Bit Error Rate (BER) through increased transmit jitter or reduced jitter tolerence.

Jitter induced by supply voltage ripple on General Purpose IO (GPIO) and PLL supplies reduces timing margin on External Memory Interfaces (EMIF) such as DDR3 and DDR4. Bit errors can be seen if timing margins are violated.

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