AN 750: Using the Altera PDN Tool to Optimize Your Power Delivery Network Design

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ID 683155
Date 7/08/2015
Public
Document Table of Contents
Document Table of Contents x
1. AN 750: Using the Altera PDN Tool to Optimize Your Power Delivery Network Design
1. AN 750: Using the Altera PDN Tool to Optimize Your Power Delivery Network Design x
1.1. Impact of a Poor PDN 1.2. PDN Circuit Topology 1.3. Estimating the Current Requirements of your FPGA Design 1.4. Calculating Ztarget 1.5. Example Design 1.6. PDN Design Optimization Study 1.7. Document Revision History
1.3. Estimating the Current Requirements of your FPGA Design x
1.3.1. FPGA Functional Blocks 1.3.2. Clock Frequencies 1.3.3. GPIO 1.3.4. Transceivers 1.3.5. Data Patterns
1.6. PDN Design Optimization Study x
1.6.1. Initial Stackup Entry 1.6.2. Using the Correct Number of Power/Ground Via Pairs 1.6.3. Using the Correct Number of Power/Ground Via Pairs and Layer Number 1.6.4. Corrected Number of Power/Ground Via Pairs and Layer Numbers 1.6.5. Moving Supplies to Optimal Layers 1.6.6. Moving Power and Ground Planes Closer Together 1.6.7. Move Decoupling Capacitors to the Top Surface of the PCB 1.6.8. Using X2Y Decoupling Capacitors 1.6.9. Using Ultra–Low ESR Bulk Capacitors 1.6.10. Swapping VCC on Layer 9 with VCC, VCCT_GXB, and VCCR_GXB on Layer 4 1.6.11. Assessing How Much Total Capacitance Might be Required 1.6.12. Using the Core Clock Frequency and Current Ramp Up Period Parameters 1.6.13. Overall Design Study Capacitor Savings 1.6.14. Overall Summary 1.6.15. References
1. AN 750: Using the Altera PDN Tool to Optimize Your Power Delivery Network Design

1.2. PDN Circuit Topology

The PDN tool is based on a lumped equivalent model representation of the power delivery network topology. A schematic representation of the circuit topology, modelled as part of the tool is shown in the figure below.

For first order analysis, the voltage regulator module (VRM) can be modelled as a series-connected resistor and inductor. At low frequencies, up to 50 KHz, the VRM has a very low impedance and is capable of responding to the instantaneous current requirements of the FPGA. The ESR and ESL values can be obtained from the VRM manufacturer. At frequencies higher than 50 KHz, the VRM impedance is mostly inductive, that makes it incapable of meeting the transient current requirement. The on-board discrete decoupling capacitors must provide the required low impedance from low to high frequencies, depending on the capacitor intrinsic parasitics (RcN, CcN, LcN) and the capacitor mounting inductance (LmntN). The interplanar capacitance between the power-ground planes typically has lower inductance than the discrete decoupling capacitor network, making it more effective at higher frequencies (10 MHz and higher). The effectiveness of the decoupling capacitors is limited by the PCB spreading inductance and the ball grid array (BGA) via inductance that a given capacitor encounters with respect to the FPGA. To simplify the circuit topology, the PDN tool models the distributed nature of PCB spreading, BGA inductance, and resistance with a single lumped inductor and resistor.

Figure 1. PDN Circuit Topology

From this diagram it is clear that the key to improving the efficiency of the PCB PDN is to reduce component mounting inductance (Lmnt), parasitic inductance (Lc) and spreading inductance (Ls). This application note will provide guidance on methods of reducing these inductances, and how to evaluate this in the PDN Tool.

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