Visible to Intel only — GUID: jba1434040192629
Ixiasoft
1.6.1. Initial Stackup Entry
1.6.2. Using the Correct Number of Power/Ground Via Pairs
1.6.3. Using the Correct Number of Power/Ground Via Pairs and Layer Number
1.6.4. Corrected Number of Power/Ground Via Pairs and Layer Numbers
1.6.5. Moving Supplies to Optimal Layers
1.6.6. Moving Power and Ground Planes Closer Together
1.6.7. Move Decoupling Capacitors to the Top Surface of the PCB
1.6.8. Using X2Y Decoupling Capacitors
1.6.9. Using Ultra–Low ESR Bulk Capacitors
1.6.10. Swapping VCC on Layer 9 with VCC, VCCT_GXB, and VCCR_GXB on Layer 4
1.6.11. Assessing How Much Total Capacitance Might be Required
1.6.12. Using the Core Clock Frequency and Current Ramp Up Period Parameters
1.6.13. Overall Design Study Capacitor Savings
1.6.14. Overall Summary
1.6.15. References
Visible to Intel only — GUID: jba1434040192629
Ixiasoft
1.3.1. FPGA Functional Blocks
The current and decoupling requirements increase if the current in your design increases.
To estimate the current requirements of your design, Altera recommends including all functional blocks that you plan to use. Include accurate use of Logic Elements, DSP blocks, PLLs, transceivers, Hard IP, HPS, Internal Memory and IO.