AN 750: Using the Altera PDN Tool to Optimize Your Power Delivery Network Design

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ID 683155
Date 7/08/2015
Public
Document Table of Contents
Document Table of Contents x
1. AN 750: Using the Altera PDN Tool to Optimize Your Power Delivery Network Design
1. AN 750: Using the Altera PDN Tool to Optimize Your Power Delivery Network Design x
1.1. Impact of a Poor PDN 1.2. PDN Circuit Topology 1.3. Estimating the Current Requirements of your FPGA Design 1.4. Calculating Ztarget 1.5. Example Design 1.6. PDN Design Optimization Study 1.7. Document Revision History
1.3. Estimating the Current Requirements of your FPGA Design x
1.3.1. FPGA Functional Blocks 1.3.2. Clock Frequencies 1.3.3. GPIO 1.3.4. Transceivers 1.3.5. Data Patterns
1.6. PDN Design Optimization Study x
1.6.1. Initial Stackup Entry 1.6.2. Using the Correct Number of Power/Ground Via Pairs 1.6.3. Using the Correct Number of Power/Ground Via Pairs and Layer Number 1.6.4. Corrected Number of Power/Ground Via Pairs and Layer Numbers 1.6.5. Moving Supplies to Optimal Layers 1.6.6. Moving Power and Ground Planes Closer Together 1.6.7. Move Decoupling Capacitors to the Top Surface of the PCB 1.6.8. Using X2Y Decoupling Capacitors 1.6.9. Using Ultra–Low ESR Bulk Capacitors 1.6.10. Swapping VCC on Layer 9 with VCC, VCCT_GXB, and VCCR_GXB on Layer 4 1.6.11. Assessing How Much Total Capacitance Might be Required 1.6.12. Using the Core Clock Frequency and Current Ramp Up Period Parameters 1.6.13. Overall Design Study Capacitor Savings 1.6.14. Overall Summary 1.6.15. References
1. AN 750: Using the Altera PDN Tool to Optimize Your Power Delivery Network Design

1. AN 750: Using the Altera PDN Tool to Optimize Your Power Delivery Network Design

This application note provides guidance on the estimation of FPGA current requirements for the design of a robust FPGA Power Delivery Network (PDN). It provides guidance on how to improve the efficiency of the PDN with the Altera PDN Tool, with an objective of reducing the number of PCB mounted decoupling capacitors.

Altera provides a PDN tool that is based on an Microsoft Excel spreadsheet used to calculate an impedance profile based on user inputs. This PDN Tool helps design a robust PDN, estimate its performance and optimize decoupling solutions and reduce cost. The PDN Tool can be used to analyze all FPGA power supply rails.

This application note should be read in conjunction with the PDN Tool User guide, and PowerPlay Early Power Estimators (EPE) and PowerPlay Power Analyzer.

For more information on PDN design refer to Printed Circuit Board (PCB) Power Delivery Network (PDN) Design Methodology and on the Altera Board Design Resource Center.


Section Content
Impact of a Poor PDN
PDN Circuit Topology
Estimating the Current Requirements of your FPGA Design
Calculating Ztarget
Example Design
PDN Design Optimization Study
Document Revision History

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