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1. About the 25G Ethernet Intel FPGA IP
2. Getting Started
3. 25G Ethernet Intel FPGA IP Parameters
4. Functional Description
5. Reset
6. Interfaces and Signal Descriptions
7. Control, Status, and Statistics Register Descriptions
8. Debugging the Link
9. 25G Ethernet Stratix® 10 Intel® FPGA IP User Guide Archives
10. Document Revision History for the 25G Ethernet Stratix® 10 Intel® FPGA IP User Guide
6.1. TX MAC Interface to User Logic
6.2. RX MAC Interface to User Logic
6.3. Transceivers
6.4. Transceiver Reconfiguration Signals
6.5. Avalon® Memory-Mapped Management Interface
6.6. PHY Interface Signals
6.7. 1588 PTP Interface Signals
6.8. Miscellaneous Status and Debug Signals
6.9. Reset Signals
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6. Interfaces and Signal Descriptions
Figure 31. 25G Ethernet Intel FPGA IP Signals and Interfaces