Visible to Intel only — GUID: lbl1457133565729
Ixiasoft
Visible to Intel only — GUID: lbl1457133565729
Ixiasoft
6.2. RX MAC Interface to User Logic
Signal |
Direction |
Description |
---|---|---|
clk_rxmac | Output | Clock for the RX MAC. Recovered from the incoming data. This clock is guaranteed stable when rx_pcs_ready is asserted. The frequency of this clock is 390.625 MHz for 25G data rate and 156.25 MHz for 10G data rate.. All RX MAC interface signals are synchronous to clk_rxmac . |
l1_rx_data[63:0] | Output | Data output from the MAC. Bit[63] is the MSB and bit[0] is the LSB. Bytes are read in the usual left to right order. The IP core reverses the byte order to meet the requirements of the Ethernet standard. |
l1_rx_valid | Output | When asserted, indicates that l1_rx_data[63:0] is driving valid data. If you turn off Enable RS-FEC , the IP core asserts this signal continuously between the assertions of l1_tx_startofpacket and l1_tx_endofpacket for the same packet. However, if you turn on Enable RS-FEC , the IP core drives IDLE cycles during alignment marker cycles. |
l1_rx_startofpacket | Output | When asserted, indicates the first byte of a frame. |
l1_rx_endofpacket | Output | When asserted, indicates the last data byte of a frame, before the frame check sequence (FCS). In CRC pass-through mode, it is the last byte of the FCS. The packet can end at any byte position. |
l1_rx_empty[2:0] | Output | Specifies the number of empty bytes when l1_rx_endofpacket is asserted. The packet can end at any byte position. The empty bytes are the low-order bytes. |
l1_rx_error[5:0] | Output | When asserted in the same cycle as l1_rx_endofpacket, indicates the current packet should be treated as an error packet. The 6 bits of l1_rx_error specify the following errors:
|
l1_rxstatus_valid | Output | When asserted, indicates that l1_rxstatus_data is driving valid data. |
l1_rxstatus_data[39:0] | Output | Specifies information about the received frame. The following fields are defined:
|
pause_receive_rx[FCQN-1:0] | Output | Each bit of pause_receive_rx[FCQN-1:0] indicates that the corresponding queue is being paused. |