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1. About the 25G Ethernet Intel FPGA IP
2. Getting Started
3. 25G Ethernet Intel FPGA IP Parameters
4. Functional Description
5. Reset
6. Interfaces and Signal Descriptions
7. Control, Status, and Statistics Register Descriptions
8. Debugging the Link
9. 25G Ethernet Stratix® 10 Intel® FPGA IP User Guide Archives
10. Document Revision History for the 25G Ethernet Stratix® 10 Intel® FPGA IP User Guide
6.1. TX MAC Interface to User Logic
6.2. RX MAC Interface to User Logic
6.3. Transceivers
6.4. Transceiver Reconfiguration Signals
6.5. Avalon® Memory-Mapped Management Interface
6.6. PHY Interface Signals
6.7. 1588 PTP Interface Signals
6.8. Miscellaneous Status and Debug Signals
6.9. Reset Signals
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9. 25G Ethernet Stratix® 10 Intel® FPGA IP User Guide Archives
For the latest and previous versions of this user guide, refer to 25G Ethernet Stratix 10 Intel FPGA IP User Guide. If an IP or software version is not listed, the user guide for the previous IP or software version applies.
IP versions are the same as the Quartus® Prime Design Suite software versions up to v19.1. From Quartus® Prime Design Suite software version 19.2 or later, IP cores have a new IP versioning scheme.