2024.06.20 |
23.4 |
20.3.1 |
Added QuestaSim* support in the description for sim/mentor/ in the IP Core Generated Files table. |
2021.09.15 |
21.1 |
19.4.0 |
Removed references to ncsim |
2021.03.29 |
21.1 |
19.4.0 |
Updated the descriptions for the following signals in Table: Signals of the 1588 Precision Time Protocol Interface:
- tx_etstamp_ins_ctrl_residence_time_calc_format
- tx_egress_timestamp_64b_data[63:0]
- tx_egress_timestamp_96b_fingerprint[(W–1):0]
- tx_egress_timestamp_64b_fingerprint[(W–1):0]
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2021.01.29 |
20.3 |
19.4.0 |
Updated the descriptions for the following signals in Table: Signals of the PHY Interface:
- tx_clkout
- tx_clkout2
- rx_clkout
- rx_clkout2
|
2020.10.12 |
20.3 |
19.4.0 |
- Added a note to the Length Checking section to state that the MAC has a counter limit of 0xFFFF starting from Quartus® Prime Pro Edition software version 20.3 onward.
- Added a note to the Transceivers section to state that the Stratix® 10 devices use the OSC_CLK_1 pin to provide the transceiver calibration clock source.
- Made editorial updates throughout the document.
|
2020.07.29 |
20.1 |
19.4.0 |
Added the channel_reset signal to Table: Reset Signals. |
2020.06.22 |
20.1 |
19.4.0 |
- Added a new section—Accessing the Native PHY Registers in L-Tile Devices.
- Renamed section title Disabling Background Calibration to Accessing the Native PHY Registers in H-Tile Devices.
- Updated the Length/Type Field Processing section.
- Update the descriptions to the following signals in Table: Avalon® Streaming TX Datapath:
- l1_tx_data[63:0]
- l1_tx_valid
- l1_tx_ready
- Removed Figure: Client to 25G Ethernet Intel FPGA IP MAC Avalon Streaming Interface.
- Added the following Figures:
- Client to 25G Ethernet Intel FPGA IP MAC Avalon® Streaming Interface when Ready Latency is 0 (1 of 2)
- Client to 25G Ethernet Intel FPGA IP MAC Avalon® Streaming Interface when Ready Latency is 0 (2 of 2)
- Client to 25G Ethernet Intel FPGA IP MAC Avalon® Streaming Interface when Ready Latency is 3 (1 of 2)
- Client to 25G Ethernet Intel FPGA IP MAC Avalon® Streaming Interface when Ready Latency is 3 (2 of 2)
|
2020.04.13 |
20.1 |
19.4.0 |
- Added a new Table: IP Core Round Trip Latency.
- Updated the following tables:
- IP Core FPGA Resource Utilization for 25G Ethernet Intel FPGA IP Core with MAC+PCS+PMA Core Variant for Stratix® 10 Devices.
- IP Core FPGA Resource Utilization for 25G Ethernet Intel FPGA IP Core with MAC+PCS Core Variant for Stratix® 10 Devices.
- Updated the Simulating the IP Core section.
- Updated the Length Checking section.
- Updated the description for l1_rx_error[5:0] Table: Avalon® Streaming RX Datapath.
- Updated the descriptions for CNTR_RX_1519toMAXB_HI, CNTR_RX_OVERSIZE_LO, and CNTR_RX_OVERSIZE_HI Table: Receive Side Statistics Registers.
- Updated the description for latency_sclk in Table: Signals of the 1588 Precision Time Protocol Interface.
- Updated the descriptions for tx_control_phy[1:0] and rx_control_phy[1:0] in Table: Signals of the PHY Interface.
- Added a note to the description of PHY_TLKIT_ACCESS in Table: PHY Registers.
|
2020.02.21 |
19.4 |
19.4.0 |
- Updated the description for frame monitoring and statistics in the 25G Ethernet Intel FPGA IP Core Supported Features section.
- Updated the Debugging the Link section.
|
2019.12.16 |
19.4 |
19.4.0 |
- Updated the description in the About the 25G Ethernet Intel FPGA IP Core section.
- Updated the description for debug and testability features in the 25G Ethernet Intel FPGA IP Core Supported Features section.
- Updated the following tables:
- IP Core FPGA Resource Utilization for 25G Ethernet Intel FPGA IP Core with MAC+PCS+PMA Core Variant for Stratix® 10 Devices.
- IP Core FPGA Resource Utilization for 25G Ethernet Intel FPGA IP Core with MAC+PCS Core Variant for Stratix® 10 Devices.
- Updated the description in the PTP Transmit Functionality section.
- Updated the descriptions for the following signals in Table: Signals of the 1588 Precision Time Protocol Interface:
- tx_etstamp_ins_ctrl_offset_timestamp[15:0]
- tx_etstamp_ins_ctrl_offset_correction_field[15:0]
- tx_etstamp_ins_ctrl_offset_checksum_field[15:0]
- tx_etstamp_ins_ctrl_offset_checksum_correction[15:0]
- Added rx_am_lock to Table: Miscellaneous Status and Debug Signals.
- Updated the description and reset value for RXMAC_CONTROL and description for LINK_FAULT in Table: RX MAC Registers.
- Added reset_status signal to Table: Avalon® Memory-Mapped Management Interface.
- Updated the Avalon® Memory-Mapped Management Interface section.
- Updated the Statistics Registers section.
- Updated for latest Intel® branding standards.
|
2019.10.11 |
19.3 |
19.3.0 |
- Updated the description in the About the 25G Ethernet Intel FPGA IP Core section.
- Updated the PHY feature description in the 25G Ethernet Intel FPGA IP Core Supported Features section.
- Updated the description in the Hardware Testing section.
- Updated the description for 0x800, 0x801, 0x802, 0x803, 0x804, 0x805, 0x834, and 0x835 in Table: Transmit Side Statistics Registers.
- Updated the descriptions for rx_block_lock and rx_pcs_ready in Table: Miscellaneous Status and Debug Signals.
|
2019.08.29 |
19.2 |
19.2.0 |
- Added PHY_TLKIT_ACCESS register to Table: PHY Registers.
- Updated the description for CNTR_RX_RUNT_LO and CNTR_RX_RUNT_HI in Table: Receive Side Statistics Registers.
- Updated the l2_rxstatus_data bits to l1_rxstatus_data bits in the Length/Type Field Processing section.
- Updated l2_rx_error[2], l2_rx_error[3], and l2_rx_error[4] to l1_rx_error[2], l1_rx_error[3], and l1_rx_error[4] in the Length Checking section.
- Updated the steps in the Disabling Background Calibration section.
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