25G Ethernet Stratix® 10 Intel® FPGA IP User Guide

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ID 683154
Date 6/20/2024
Public
Document Table of Contents
Document Table of Contents x
1. About the 25G Ethernet Intel FPGA IP 2. Getting Started 3. 25G Ethernet Intel FPGA IP Parameters 4. Functional Description 5. Reset 6. Interfaces and Signal Descriptions 7. Control, Status, and Statistics Register Descriptions 8. Debugging the Link 9. 25G Ethernet Stratix® 10 Intel® FPGA IP User Guide Archives 10. Document Revision History for the 25G Ethernet Stratix® 10 Intel® FPGA IP User Guide
1. About the 25G Ethernet Intel FPGA IP x
1.1. Release Information 1.2. Features 1.3. 25G Ethernet Intel FPGA IP Core Device Family and Speed Grade Support 1.4. IP Core Verification 1.5. Performance and Resource Utilization
1.3. 25G Ethernet Intel FPGA IP Core Device Family and Speed Grade Support x
1.3.1. 25G Ethernet Intel FPGA IP Core Device Family Support 1.3.2. 25G Ethernet Intel FPGA IP Core Device Speed Grade Support
1.4. IP Core Verification x
1.4.1. Simulation Environment 1.4.2. Compilation Checking 1.4.3. Hardware Testing
2. Getting Started x
2.1. Installing and Licensing Intel® FPGA IP Cores 2.2. Specifying the Stratix® 10 IP Core Parameters and Options 2.3. Simulating the IP Core 2.4. Generated File Structure 2.5. Integrating Your IP Core in Your Design 2.6. Compiling the Full Design and Programming the FPGA
2.1. Installing and Licensing Intel® FPGA IP Cores x
2.1.1. Intel® FPGA IP Evaluation Mode
2.5. Integrating Your IP Core in Your Design x
2.5.1. Pin Assignments 2.5.2. Adding the Transceiver PLL 2.5.3. Adding the External Time-of-Day Module for Variations with 1588 PTP Feature 2.5.4. Placement Settings for the Core
4. Functional Description x
4.1. 25G Ethernet Intel FPGA IP Core Functional Description 4.2. User Interface to Ethernet Transmission
4.1. 25G Ethernet Intel FPGA IP Core Functional Description x
4.1.1. 25G Ethernet Intel FPGA IP Core TX MAC Datapath 4.1.2. 25 GbE TX PCS 4.1.3. TX RS-FEC 4.1.4. 25G Ethernet Intel FPGA IP Core RX MAC Datapath 4.1.5. Link Fault Signaling Interface 4.1.6. 25 GbE RX PCS 4.1.7. RX RS-FEC 4.1.8. Flow Control 4.1.9. 1588 Precision Time Protocol Interfaces
4.1.1. 25G Ethernet Intel FPGA IP Core TX MAC Datapath x
4.1.1.1. Frame Padding 4.1.1.2. Preamble Insertion 4.1.1.3. Inter-Packet Gap Generation and Insertion 4.1.1.4. Frame Check Sequence (CRC32) Insertion
4.1.4. 25G Ethernet Intel FPGA IP Core RX MAC Datapath x
4.1.4.1. IP Core Preamble Processing 4.1.4.2. IP Core Malformed Packet Handling 4.1.4.3. Length/Type Field Processing 4.1.4.4. RX CRC Checking and Dynamic Forwarding
4.1.4.3. Length/Type Field Processing x
4.1.4.3.1. Length Checking
4.1.8. Flow Control x
4.1.8.1. TX Pause/PFC Flow Control Frame Transmission Request 4.1.8.2. XON/XOFF Pause Frames
4.1.9. 1588 Precision Time Protocol Interfaces x
4.1.9.1. Implementing a 1588 System That Includes a 25G Ethernet Intel FPGA IP Core 4.1.9.2. PTP Transmit Functionality 4.1.9.3. PTP Receive Functionality 4.1.9.4. External Time-of-Day Module for 1588 PTP Variations 4.1.9.5. PTP Timestamp and TOD Formats 4.1.9.6. Design Considerations in PTP
4.2. User Interface to Ethernet Transmission x
4.2.1. Order of Transmission 4.2.2. Bit Order For TX and RX Datapaths
6. Interfaces and Signal Descriptions x
6.1. TX MAC Interface to User Logic 6.2. RX MAC Interface to User Logic 6.3. Transceivers 6.4. Transceiver Reconfiguration Signals 6.5. Avalon® Memory-Mapped Management Interface 6.6. PHY Interface Signals 6.7. 1588 PTP Interface Signals 6.8. Miscellaneous Status and Debug Signals 6.9. Reset Signals
6.4. Transceiver Reconfiguration Signals x
6.4.1. Accessing the Native PHY Registers in H-Tile Devices 6.4.2. Accessing the Native PHY Registers in L-Tile Devices
7. Control, Status, and Statistics Register Descriptions x
7.1. PHY Registers 7.2. TX MAC Registers 7.3. RX MAC Registers 7.4. Pause/PFC Flow Control Registers 7.5. Statistics Registers 7.6. 1588 PTP Registers 7.7. TX Reed-Solomon FEC Registers 7.8. RX Reed-Solomon FEC Registers
7.5. Statistics Registers x
7.5.1. TX Statistics Registers 7.5.2. RX Statistics Registers
8. Debugging the Link x
8.1. Error Insertion Test and Debugging
1. About the 25G Ethernet Intel FPGA IP
2. Getting Started
3. 25G Ethernet Intel FPGA IP Parameters
4. Functional Description
5. Reset
6. Interfaces and Signal Descriptions
7. Control, Status, and Statistics Register Descriptions
8. Debugging the Link
9. 25G Ethernet Stratix® 10 Intel® FPGA IP User Guide Archives
10. Document Revision History for the 25G Ethernet Stratix® 10 Intel® FPGA IP User Guide

2.5.2. Adding the Transceiver PLL

The transceiver channels in the Stratix® 10 devices require an external PLL to drive the TX transceiver serial clock, in order to compile and to function correctly in hardware. In many cases, the same PLL can be shared with an additional transceiver in your design.

Figure 9. PLL Configuration Example for 25G ConfigurationThe TX transceiver PLL is instantiated with an ATX PLL IP core. The TX transceiver PLL must always be instantiated outside the 25G Ethernet Intel FPGA IP core.
Figure 10. PLL Configuration Example for 10G/25G ConfigurationThe TX transceiver PLL is instantiated with an ATX PLL IP core. The TX transceiver PLL must always be instantiated outside the 25G Ethernet Intel FPGA IP core.

You can use the IP Catalog to create a transceiver PLL.

  • Select L-Tile/H-Tile Transceiver ATX PLL Stratix® 10 FPGA IP.
  • In the parameter editor, set the following parameter values:
    • For 25G configuration:
      • PLL output frequency to 12890.625 MHz. The transceiver performs dual edge clocking, using both the rising and falling edges of the input clock from the PLL. Therefore, this PLL output frequency setting supports a 25.78125 Gbps data rate through the transceiver.
      • Primary PLL clock output buffer to GXT clock output buffer.
      • Turn on Enable GXT local clock output port (tx_serial_clk_gxt).
    • For 10G configuration:
      • PLL output frequency to 5156.25 MHz. The transceiver performs dual edge clocking, using both the rising and failing edges of the input clock from the PLL. Therefore, this PLL output frequency setting supports a 10.3125 Gbps data rate through the transceiver.
      • Primary PLL clock output buffer to GX clock output buffer.
      • Turn on Enable GX local clock output port (tx_serial_clk).
    • PLL auto mode reference clock frequency (integer) to 644.53125 or 322.265625 MHz.

You must connect the ATX PLL to the 25G Ethernet Intel FPGA IP core as follows:

  • Connect the clock output port of the ATX PLL to the tx_serial_clk input port of the 25G Ethernet Intel FPGA IP core.
  • If the Enable 10G/25G dynamic rate switching option is turned on:
    • Connect the clock output port of the ATX PLL with 25G configuration to tx_serial_clk0 input port of the 25G Ethernet Intel FPGA IP core.
    • Connect the clock output port of the ATX PLL with 10G configuration to tx_serial_clk1 input port of the 25G Ethernet Intel FPGA IP core.
  • Connect the pll_locked output port of the ATX PLL to the tx_pll_locked input port of the 25G Ethernet Intel FPGA IP core.
  • Drive the ATX PLL reference clock port and the 25G Ethernet Intel FPGA IP core clk_ref input port with the same clock. The clock frequency must be the frequency you specify for the ATX PLL IP core PLL auto mode reference clock frequency (integer) parameter.
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