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1. About the DIB Intel® Stratix® 10 FPGA IP User Guide
2. About the DIB Intel® Stratix® 10 FPGA IP
3. Functional Description
4. Creating and Parameterizing the Intel FPGA IP
5. Designing with the DIB Intel® Stratix® 10 FPGA IP
6. DIB Intel® Stratix® 10 FPGA IP Interface
7. DIB Intel® Stratix® 10 FPGA IP Parameters
8. Document Revision History for the DIB Intel® Stratix® 10 FPGA IP User Guide
A. Die-to-Die Mapping
B. Example Pin Locations for One DIB Channel
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3.1.1. AUX Channel Settings
You can enable any combination settings for the AUX channel with certain restrictions.
Follow these restrictions:
- Banks 0 and 3 are 22 bits wide and configurable as TX or RX.
- Bank 1 has a total width of 17 bits:
- 16 bits are for TX data only
- 1 bit is reserved for clock
- Bank 2 has a total width of 17 bits:
- 16 bits are for RX data only
- 1 bit is reserved for clock
Figure 6. AUX Channel Settings