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1. About the DIB Intel® Stratix® 10 FPGA IP User Guide
2. About the DIB Intel® Stratix® 10 FPGA IP
3. Functional Description
4. Creating and Parameterizing the Intel FPGA IP
5. Designing with the DIB Intel® Stratix® 10 FPGA IP
6. DIB Intel® Stratix® 10 FPGA IP Interface
7. DIB Intel® Stratix® 10 FPGA IP Parameters
8. Document Revision History for the DIB Intel® Stratix® 10 FPGA IP User Guide
A. Die-to-Die Mapping
B. Example Pin Locations for One DIB Channel
Visible to Intel only — GUID: ruu1588914653057
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6. DIB Intel® Stratix® 10 FPGA IP Interface
All the interfaces for each DIB channel are always present. Unused signals are not connected.
The DIB Intel® Stratix® 10 FPGA IP has three main interface signals:
- Control
- Data
- DIB Pad
The direction of the DIB pad signals are dynamically generated based on your settings in the parameter editor.
All standard and AUX channels have the same top-level signals.
Top-Level Signals for Each DIB Channel
module my_dib (
output wire [81:0] core_rx_data_0,
output wire [81:0] core_rx_data_1,
output wire [81:0] core_rx_data_2,
output wire [81:0] core_rx_data_3,
input wire [81:0] core_tx_data_0,
input wire [81:0] core_tx_data_1,
input wire [81:0] core_tx_data_2,
input wire [81:0] core_tx_data_3,
input wire dib_clk,
output wire dib_ready_n,
input wire iopll_locked,
input wire [23:0] dib_pad_0,
output wire [23:0] dib_pad_1,
input wire [23:0] dib_pad_2,
output wire [23:0] dib_pad_3,
output wire rem_clk,
input wire sys_clk
);
endmodule