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1. About the DIB Intel® Stratix® 10 FPGA IP User Guide
2. About the DIB Intel® Stratix® 10 FPGA IP
3. Functional Description
4. Creating and Parameterizing the Intel FPGA IP
5. Designing with the DIB Intel® Stratix® 10 FPGA IP
6. DIB Intel® Stratix® 10 FPGA IP Interface
7. DIB Intel® Stratix® 10 FPGA IP Parameters
8. Document Revision History for the DIB Intel® Stratix® 10 FPGA IP User Guide
A. Die-to-Die Mapping
B. Example Pin Locations for One DIB Channel
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6.1. DIB Intel® Stratix® 10 FPGA IP Clocks
The DIB Intel® Stratix® 10 FPGA IP mainly uses four clock signals.
Signals | Direction | Description | Mode | ||
---|---|---|---|---|---|
Bypass | Asynchronous | Synchronous | |||
dib_clk | Input | Clocks the inter-die logic. | Tie this signal high (not used). | Tie to the DIB clock (used for TX banks). | Tie to the DIB clock (used for TX banks). |
sys_clk | Input | Ratio to the dib_clk signal set to Hard TDM ratio. Drives the soft TDM interface logic to the DIB Interface IP. | Tie this signal high (not used). | Tie this signal high (not used). | Tie this signal to the same PLL source as the DIB clock ratio set to the Hard TDM ratio (used for TX banks). |
dut_clk | Input | Input clock for the standard DIB channel. | Tie this signal high (not used). | Tie this signal to the DUT clock (synchronous to the DIB clock). | Tie this signal high (not used). |
Input clock for the AUX DIB channel. | Tie this signal to the DUT clock (used for TX banks). | Not applicable. | Not applicable. | ||
rem_clk | Output | Output clock for the standard DIB channel. | Not used. | Not used. | Divided version of the DIB clock forwarded for the TX die (used as system clock on the RX banks). |
Output clock for the AUX DIB channel. | DUT clock forwarded from the TX die. | Not applicable. | Not applicable. |