Visible to Intel only — GUID: xws1589511089165
Ixiasoft
1. About the DIB Intel® Stratix® 10 FPGA IP User Guide
2. About the DIB Intel® Stratix® 10 FPGA IP
3. Functional Description
4. Creating and Parameterizing the Intel FPGA IP
5. Designing with the DIB Intel® Stratix® 10 FPGA IP
6. DIB Intel® Stratix® 10 FPGA IP Interface
7. DIB Intel® Stratix® 10 FPGA IP Parameters
8. Document Revision History for the DIB Intel® Stratix® 10 FPGA IP User Guide
A. Die-to-Die Mapping
B. Example Pin Locations for One DIB Channel
Visible to Intel only — GUID: xws1589511089165
Ixiasoft
5.1. Reset Architecture
The DIB subsystem is either in freeze mode or user mode.
Upon power-up, the DIB subsystem enters freeze mode. All the freeze signals from the DIB subsystem get asserted when the system asserts the power-on reset signal. During freeze mode, the DIB subsystem is in a safe state and all interface signals to the core fabric are driven high.
During freeze mode, the DIB I/Os are tri-stated, and the DIB SSM configures the entire DIB subsystem.
For the Intel® Stratix® 10 GX 10M variant, the external reset is controlled by user logic or your system design.
- You must track all the dib_ready pins from both dies to determine that both Intel® Stratix® 10 GX 10M variants are ready for data transactions.
- You should enable the external reset only after all the dib_ready_n pins are asserted.
- Only after enabling the external reset, you enable the cross-die transactions.