6.2. DIB Intel® Stratix® 10 FPGA IP User Interface Signals
Signal | Width | Direction | Description |
---|---|---|---|
iopll_locked | 1 | Input | When you set the DIB Channel Type parameter to Standard Channel, this signal connects to locked IOPLL when using a bank with TDM. This signal is not applicable if you select AUX Channel. |
dib_ready_n | 1 | Output | This signal goes low when the DIB channel is ready. |
Signal | Width | Direction | Description |
---|---|---|---|
dib_pad_0 | 24 | Input/Output | DIB pads for bank 0. The direction of this signal depends on the mode of I/O bank 0. |
dib_pad_1 | 24 | Input/Output | DIB pads for bank 1. The direction of this signal depends on the mode of I/O bank 1. |
dib_pad_2 | 24 | Input/Output | DIB pads for bank 2. The direction of this signal depends on the mode of I/O bank 2. |
dib_pad_3 | 24 | Input/Output | DIB pads for bank 3. The direction of this signal depends on the mode of I/O bank 3. |
Signal | Width | Direction | Description |
---|---|---|---|
core_rx_data_0 | 82 | Output | Core data RX interface for bank 0.
The direction of this signal depends on the mode of I/O bank 0. |
core_rx_data_1 | 82 | Output | Core data RX interface for bank 1.
The direction of this signal depends on the mode of I/O bank 0. |
core_rx_data_2 | 82 | Output | Core data RX interface for bank 2.
The direction of this signal depends on the mode of I/O bank 0. |
core_rx_data_3 | 82 | Output | Core data RX interface for bank 3.
The direction of this signal depends on the mode of I/O bank 0. |
Signal | Width | Direction | Description |
---|---|---|---|
core_rx_data_0 | 82 | Input | Core data TX interface for bank 0.
The direction of this signal depends on the mode of I/O bank 0. |
core_rx_data_1 | 82 | Input | Core data TX interface for bank 1.
The direction of this signal depends on the mode of I/O bank 0. |
core_rx_data_2 | 82 | Input | Core data TX interface for bank 2.
The direction of this signal depends on the mode of I/O bank 0. |
core_rx_data_3 | 82 | Input | Core data TX interface for bank 3.
The direction of this signal depends on the mode of I/O bank 0. |