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1. About the DIB Intel® Stratix® 10 FPGA IP User Guide
2. About the DIB Intel® Stratix® 10 FPGA IP
3. Functional Description
4. Creating and Parameterizing the Intel FPGA IP
5. Designing with the DIB Intel® Stratix® 10 FPGA IP
6. DIB Intel® Stratix® 10 FPGA IP Interface
7. DIB Intel® Stratix® 10 FPGA IP Parameters
8. Document Revision History for the DIB Intel® Stratix® 10 FPGA IP User Guide
A. Die-to-Die Mapping
B. Example Pin Locations for One DIB Channel
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8. Document Revision History for the DIB Intel® Stratix® 10 FPGA IP User Guide
Document Version | Intel® Quartus® Prime Version | Intel® FPGA IP Version | Changes |
---|---|---|---|
2021.03.18 | 20.2 | 19.3.0 | Updated the description for periphery-to-core transfer (RX side) in Table: Timing Transfer for TDM Modes. |
2020.12.07 | 20.2 | 19.3.0 |
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2020.08.30 | 20.2 | 19.3.0 |
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2020.06.30 | 20.2 | 19.3.0 | Initial release. |