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1. About the DIB Intel® Stratix® 10 FPGA IP User Guide
2. About the DIB Intel® Stratix® 10 FPGA IP
3. Functional Description
4. Creating and Parameterizing the Intel FPGA IP
5. Designing with the DIB Intel® Stratix® 10 FPGA IP
6. DIB Intel® Stratix® 10 FPGA IP Interface
7. DIB Intel® Stratix® 10 FPGA IP Parameters
8. Document Revision History for the DIB Intel® Stratix® 10 FPGA IP User Guide
A. Die-to-Die Mapping
B. Example Pin Locations for One DIB Channel
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2.3. DIB Intel® Stratix® 10 FPGA IP Features
The DIB Intel® Stratix® 10 FPGA IP offers three modes of operation: Bypass, Asynchronous, and Synchronous.
The DIB Intel® Stratix® 10 FPGA IP includes the following features:
- Time-division multiplexing (TDM) ratio
- Asynchronous mode: 1:1, 2:1, or 4:1
- Synchronous mode: 1:1, 2:1, or 4:1
- Maximum transfer clock rate of 400 MHz (Asynchronous and Synchronous modes)
- Bypass transfer latency of 2.5 ns (through direct interface bus only)
- Three subsystems; each subsystem consists of 24 standard channels and 1 AUX channel
- Four banks per channel
- Maximum 22 I/Os per bank for Bypass mode and 20 I/Os for Asynchronous and Synchronous modes
- Read and Write I/Os set per bank
Mode | TDM Ratio | Total I/Os |
---|---|---|
Bypass | Not applicable | 6,564 |
Asynchronous or Synchronous | 1:1 | 5,760 |
2:1 | 11,520 | |
4:1 | 23,040 |