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1. About the DIB Intel® Stratix® 10 FPGA IP User Guide
2. About the DIB Intel® Stratix® 10 FPGA IP
3. Functional Description
4. Creating and Parameterizing the Intel FPGA IP
5. Designing with the DIB Intel® Stratix® 10 FPGA IP
6. DIB Intel® Stratix® 10 FPGA IP Interface
7. DIB Intel® Stratix® 10 FPGA IP Parameters
8. Document Revision History for the DIB Intel® Stratix® 10 FPGA IP User Guide
A. Die-to-Die Mapping
B. Example Pin Locations for One DIB Channel
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5.4. Setting Bypass, Asynchronous, and Synchronous Modes in One DIB Instance
You may set each bank, in a channel of four banks, to different DIB modes.
However, be mindful of the following limitations:
- If you set bank 0 to RX in Bypass mode, and any of the other banks to RX in Asynchronous or Synchronous mode, then pad_0_dib_pad[22] pin cannot be timed, and therefore cannot be used.
- If you set bank 3 to TX in Bypass mode, and any of the other banks to TX in Asynchronous or Synchronous mode, then pad_3_dib_pad[22] pin cannot be timed, and therefore cannot be used.
Note: In these situations, the Intel® Quartus® Prime software displays a warning message in the parameter editor and flags a critical warning in the Fitter.