Direct Interface Bus (DIB) Intel® Stratix® 10 FPGA IP User Guide

ID 683142
Date 3/18/2021
Public
Document Table of Contents

5.4. Setting Bypass, Asynchronous, and Synchronous Modes in One DIB Instance

You may set each bank, in a channel of four banks, to different DIB modes.
However, be mindful of the following limitations:
  • If you set bank 0 to RX in Bypass mode, and any of the other banks to RX in Asynchronous or Synchronous mode, then pad_0_dib_pad[22] pin cannot be timed, and therefore cannot be used.
  • If you set bank 3 to TX in Bypass mode, and any of the other banks to TX in Asynchronous or Synchronous mode, then pad_3_dib_pad[22] pin cannot be timed, and therefore cannot be used.
Note: In these situations, the Intel® Quartus® Prime software displays a warning message in the parameter editor and flags a critical warning in the Fitter.