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1. Acronyms
2. Introduction
3. IP Architecture and Functional Description
4. Advanced Features
5. Interfaces
6. Parameters
7. Testbench
8. Troubleshooting/Debugging
9. F-Tile Avalon Streaming Intel FPGA IP for PCI Express User Guide Archives
10. Revision History for the F-Tile Avalon Streaming Intel FPGA IP for PCI Express User Guide
A. Configuration Space Registers
B. Implementation of Address Translation Services (ATS) in Endpoint Mode
C. Packets Forwarded to the User Application in TLP Bypass Mode
D. Root Port Enumeration
E. Bifurcated Endpoint Support for Independent Resets
3.1. Architecture
3.2. Functional Description
3.3. Avalon-ST TX/RX
3.4. Interrupts
3.5. Completion Timeout
3.6. Hot Plug
3.7. Power Management
3.8. Configuration Output Interface (COI)
3.9. Configuration Intercept Interface (EP Only)
3.10. Hard IP Reconfiguration Interface
3.11. PHY Reconfiguration Interface
3.12. Page Request Service (PRS) (EP Only)
5.1. Overview
5.2. Clocks and Resets
5.3. Serial Data Interface
5.4. Avalon-ST Interface
5.5. Interrupt Interface
5.6. Hard IP Status Interface
5.7. Error Interface
5.8. 10-bit Tag Support Interface
5.9. Completion Timeout Interface
5.10. Power Management Interface
5.11. Hot Plug Interface (RP Only)
5.12. Configuration Output Interface
5.13. Configuration Intercept Interface (EP Only)
5.14. Hard IP Reconfiguration Interface
5.15. PHY Reconfiguration Interface
5.16. Page Request Service (PRS) Interface (EP Only)
5.17. FLR Interface Signals
5.18. PTM Interface Signals
5.19. VF Error Flag Interface Signals
5.20. VirtIO PCI Configuration Access Interface Signals
6.2.3.1. Device Capabilities
6.2.3.2. Link Capabilities
6.2.3.3. Legacy Interrupt Pin Register
6.2.3.4. MSI Capabilities
6.2.3.5. MSI-X Capabilities
6.2.3.6. Slot Capabilities
6.2.3.7. Latency Tolerance Reporting (LTR)
6.2.3.8. Process Address Space ID (PASID)
6.2.3.9. Device Serial Number Capability
6.2.3.10. Page Request Service (PRS)
6.2.3.11. Access Control Service (ACS) Capabilities
6.2.3.12. Power Management
6.2.3.13. Vendor Specific Extended Capability (VSEC) Registers
6.2.3.14. Precision Time Measurement (PTM)
6.2.3.15. Address Translation Services (ATS)
6.2.3.16. TLP Processing Hints (TPH)
6.2.3.17. VirtIO Parameters
6.2.3.18. Receiver Detection
7.6.1. ebfm_barwr Procedure
7.6.2. ebfm_barwr_imm Procedure
7.6.3. ebfm_barrd_wait Procedure
7.6.4. ebfm_barrd_nowt Procedure
7.6.5. ebfm_cfgwr_imm_wait Procedure
7.6.6. ebfm_cfgwr_imm_nowt Procedure
7.6.7. ebfm_cfgrd_wait Procedure
7.6.8. ebfm_cfgrd_nowt Procedure
7.6.9. BFM Configuration Procedures
7.6.10. BFM Shared Memory Access Procedures
7.6.11. BFM Log and Message Procedures
7.6.12. Verilog HDL Formatting Functions
A.3.1. Intel-Defined VSEC Capability Header (Offset 00h)
A.3.2. Intel-Defined Vendor Specific Header (Offset 04h)
A.3.3. Intel Marker (Offset 08h)
A.3.4. JTAG Silicon ID (Offset 0x0C - 0x18)
A.3.5. User Configurable Device and Board ID (Offset 0x1C - 0x1D)
A.3.6. General Purpose Control and Status Register (Offset 0x30)
A.3.7. Uncorrectable Internal Error Status Register (Offset 0x34)
A.3.8. Uncorrectable Internal Error Mask Register (Offset 0x38)
A.3.9. Correctable Internal Error Status Register (Offset 0x3C)
A.3.10. Correctable Internal Error Mask Register (Offset 0x40)
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2.2. Features
The F-Tile Avalon® Streaming Interface for PCI Express supports the following features:
PCIe* Features
- Complete protocol stack including the Transaction, Data Link and Physical Layers implemented as a Hard IP.
- Topologies supported:
Table 2. Topologies Supported Gen3/Gen4 x16 Gen3/Gen4 x8 Gen3/Gen4 x4 Endpoint Yes
Yes
Yes
Root Port Yes
Yes
Yes
TLP-Bypass Yes
Yes
Yes
Note: Gen1/Gen2 or lower link width configurations are supported via link down-training - Supports up to 512-byte maximum payload size (MPS).
- Supports Single Virtual Channel (VC).
- Supports Completion Timeout Ranges through Completion Timeout Interface
- Atomic Operations (FetchAdd/Swap/CAS).
- Extended Tag Support. (10-bit Tag Support Applies to x16 ports only. Maximum 512 Outstanding Non-Posted Request).
- Separate Refclk with Independent Spread Spectrum Clocking (SRIS).
- Separate Refclk with no Spread Spectrum Clocking (SRNS).
- Common Refclk architecture.
- PCI Express* Advanced Error Reporting (Physical Function only).
- ECRC generation and checking.
- Data bus parity protection.
- Supports D0 and D3 PCIe power states.
- Lane Margining at Receiver.
- Retimers presence detection.
Multifunction and Virtualization Features:
- Single Root-IO Virtualization (SR-IOV). Up to 2048 Virtual Functions.
- ACS Control Service (ACS) capability support for Port 0 and 1 (x16 Core and x8 Core)
- Alternative Routing-ID Interpretation (ARI).
- Function Level Reset (FLR).
- TLP Processing Hint (TPH).
Note: TPH supports the "No Steering Tag (ST)" mode only.
- Address Translation Services (ATS)
- Supports Page Request Services (PRS).
- Process Address Space ID (PASID).
- Configuration Intercept Interface (for VirtIO).
Avalon® Streaming Interface IP Features:
- User packet interface with separate header, data and prefix.
- User packet interface with a split-bus architecture where the header, data and prefix busses consist of two segments each (x16 mode only). This improves the bandwidth efficiency of this interface as it can handle up to 2 TLPs in any given cycle.
- Up to 512 outstanding Non-Posted request for Port 0 (x16 core).
- Up to 256 outstanding Non-Posted request for Port 1,2 and 3 (x8 and x4 cores).
- Supports Autonomous Hard IP mode. This mode allows the PCIe Hard IP to communicate with the Host before the FPGA configuration and entry into user mode are complete.
Note: Unless Readiness Notifications mechanisms are used, the Root Complex and/or system software must allow at least one second after a Conventional Reset of a device before it may determine that a device that fails to return a Successful Completion status for a valid Configuration Request is a broken device. This period is independent of how quickly Link training is complete.
- FPGA core configuration via PCIe link (CvP Init and CvP Update) supported by the x16 Core for Port 0 only. Refer to the Agilex 7 Device Configuration via Protocol (CvP) Implementation User Guide for more information.
- Variable PLD clock frequencies: (500 MHz/ 450 MHz / 400 MHz / 350 MHz / 250 MHz / 225 MHz / 200 MHz /175 MHz for Agilex™ 7).
- Legacy Interrupts.
- MSI/MSI-X interrupts.
- Configuration Extension Bus & VSEC via CII interface.
Note: CII Interface is not supported for 1 x4 configuration or Topology H.
- Precision Time Measurement (PTM) (PTM Requester only)
Note: You can enable PTM only in one core (either x16 or x8) at any given time.
- Parity Support on Avalon-ST interface.
- The FPGA pin allocations for the F-Tile Avalon Streaming IP for PCI Express in the Quartus® Prime project is fixed. However, this IP does support lane reversal and polarity inversion on the PCB by default.
- VCS* , VCS* MX, QuestaSim* , Xcelium* , and Riviera-PRO* are the simulators supported in the current Quartus® Prime release. Other simulators may be supported in a future release.
Standards and Specification Compliance
- PCI Express Base Specification Revision 4.0
- Single Root I/O Virtualization and Sharing Specification, Rev 1.1
- Address Translation Services, Revision 1.1
- PHY Interface for PCI Express Architectures, Version 4.x (the spec that corresponds to PCI Express Base Spec, Revision 4.0)
- Virtual I/O Device (VIRTIO) Version 1.0
Note: Throughout this User Guide, the term AVST or Avalon-ST may be used as an abbreviation for the Avalon® Streaming Interface IP.
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