Nios® II Flash Programmer User Guide

ID 683118
Date 11/06/2017
Public
Document Table of Contents

2.5. Checking System ID and System Timestamp

If your flash programmer target design includes a System ID component, the Nios® II Flash Programmer can perform system ID and system timestamp checking before programming flash memory. If the flash programmer performs system ID checking, system timestamp checking, or both, and the expected system is not configured in the FPGA, the flash programmer does not program the flash memory.
Note: The system ID and system timestamp checking are enabled by default. Intel recommends you keep these settings and that your FPGA target design include a system ID component.

To disable checking for system ID or system timestamp, perform the following steps:

  1. Click Hardware Connections. The Hardware Connections dialog box appears.
  2. To disable system ID checking, turn on Ignore mismatched system ID.
  3. To disable system timestamp checking, turn on Ignore mismatched system timestamp.
  4. Click Close.
After the hardware connections are set, you can confirm system ID and system timestamp matching by performing the following steps:
  1. Click Hardware Connections.
  2. In the Hardware Connections dialog box, click System ID Properties.
  3. Check that the Expected system ID and Actual system ID values match, and that the Expected system timestamp and Actual system timestamp values match.
  4. In the System ID Properties dialog box, click Close.
  5. In the Hardware Connections dialog box, click Close.

For additional information about the system ID and system timestamp, refer to the "General Parameters" table in the "quartus_pgm --nios 2 Parameters" section.

Regardless of the System ID component values, you cannot program flash memory if the hardware design configured in the FPGA is not a valid flash programmer target design that contains at least the minimum component set. Refer to Table: Minimum Component Set for the Flash Programmer Target Design in the Flash Programmer Target Design chapter.