DisplayPort Intel® Arria 10 FPGA IP Design Example User Guide

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ID 683050
Date 11/12/2021
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Document Table of Contents
Document Table of Contents x
1. DisplayPort Intel® FPGA IP Design Example Quick Start Guide 2. Parallel Loopback Design Examples 3. HDCP Over DisplayPort Design Example for Intel® Arria® 10 Devices 4. DisplayPort Intel® Arria® 10 FPGA IP Design Example User Guide Archives 5. Revision History for DisplayPort Intel® Arria® 10 FPGA IP Design Example User Guide
1. DisplayPort Intel® FPGA IP Design Example Quick Start Guide x
1.1. Directory Structure 1.2. Hardware and Software Requirements 1.3. Generating the Design 1.4. Simulating the Design 1.5. Compiling and Testing the Design 1.6. DisplayPort Intel® FPGA IP Design Example Parameters
1.5. Compiling and Testing the Design x
1.5.1. Regenerating ELF File
2. Parallel Loopback Design Examples x
2.1. Intel® Arria® 10 DisplayPort SST Parallel Loopback Design Features 2.2. Intel® Arria® 10 DisplayPort MST Parallel Loopback Design Features 2.3. Enabling Adaptive Sync Support 2.4. Creating RX-Only or TX-Only Designs 2.5. Design Components 2.6. Clocking Scheme 2.7. Interface Signals and Parameters 2.8. Hardware Setup 2.9. Simulation Testbench 2.10. DisplayPort Transceiver Reconfiguration Flow 2.11. Transceiver Lane Configurations
3. HDCP Over DisplayPort Design Example for Intel® Arria® 10 Devices x
3.1. High-bandwidth Digital Content Protection (HDCP) 3.2. HDCP Over DisplayPort Design Example Architecture 3.3. Nios II Processor Software Flow 3.4. Design Walkthrough 3.5. Protection of Encryption Key Embedded in FPGA Design 3.6. Debug Guidelines
3.4. Design Walkthrough x
3.4.1. Set Up the Hardware 3.4.2. Generate the Design 3.4.3. Include HDCP Production Keys 3.4.4. Compile the Design 3.4.5. View the Results
3.4.3. Include HDCP Production Keys x
3.4.3.1. Store plain HDCP production keys in the FPGA (Support HDCP Key Management = 0) 3.4.3.2. Store encrypted HDCP production keys in the external flash memory or EEPROM (Support HDCP Key Management = 1)
3.4.3.1. Store plain HDCP production keys in the FPGA (Support HDCP Key Management = 0) x
3.4.3.1.1. HDCP Key Mapping from DCP Key Files 3.4.3.1.2. hdcp1x_tx_kmem.v and hdcp1x_rx_kmem.v files 3.4.3.1.3. hdcp2x_rx_kmem.v file 3.4.3.1.4. hdcp2x_tx_kmem.v file
3.4.3.2. Store encrypted HDCP production keys in the external flash memory or EEPROM (Support HDCP Key Management = 1) x
3.4.3.2.1. Intel KEYENC 3.4.3.2.2. Key Programmer
3.4.5. View the Results x
3.4.5.1. LED Functions
3.5. Protection of Encryption Key Embedded in FPGA Design x
3.5.1. Security Considerations
3.6. Debug Guidelines x
3.6.1. HDCP Status Signals 3.6.2. Modifying HDCP Software Parameters 3.6.3. Frequently Asked Questions (FAQ)
1. DisplayPort Intel® FPGA IP Design Example Quick Start Guide
2. Parallel Loopback Design Examples
3. HDCP Over DisplayPort Design Example for Intel® Arria® 10 Devices
4. DisplayPort Intel® Arria® 10 FPGA IP Design Example User Guide Archives
5. Revision History for DisplayPort Intel® Arria® 10 FPGA IP Design Example User Guide

5. Revision History for DisplayPort Intel® Arria® 10 FPGA IP Design Example User Guide

Document Version Intel® Quartus® Prime Version Intel® FPGA IP Version Changes
2021.11.12 21.3 19.4.0
  • Replaced AN556 to AN556: Using the DesignSecurity Features in Intel FPGAs in Protection of Encryption Key Embedded in FPGA Design.
  • Updated the subsection Store encrypted HDCP production keys in the external flash memory or EEPROM (Support HDCP Key Management = 1) to describe the new key encryption software utility (KEYENC).
  • Removed the following figures:
    • Data array of Facsimile Key R1 for RX Private Key
    • Data arrays of HDCP Production Keys (Placeholder)
    • Data array of HDCP Protection Key (Predefined key)
    • HDCP protection key initialized in hdcp2x_tx_kmem.mif
    • HDCP protection key initialized in hdcp1x_rx_kmem.mif
    • HDCP protection key initialized in hdcp1x_tx_kmem.mif
  • Moved subsection HDCP Key Mapping from DCP Key Files from Debug Guidelines to Store plain HDCP production keys in the FPGA (Support HDCP Key Management = 0).
2021.09.15 21.1 19.4.0 Removed referenes to ncsim
2021.05.11 21.1 19.4.0
  • Added SUPPORT HDCP KEY MANAGEMENT = 1 to the description for Figure : HDCP Over DisplayPort Design Example Block Diagram.
  • Added the steps in HDCP over DisplayPort design example in Design Walkthrough.
  • Added the step to turn on Support HDCP Key Management parameter in Generate the Design.
  • Added a new subsection Store encrypted HDCP production keys in the external flash memory or EEPROM (Support HDCP Key Management = 1).
  • Added a new chapter Protection of Encryption Key Embedded in FPGA Design.
  • Added a new chapter Debug Guidelines and subsection HDCP Status Signals, Modifying HDCP Software Parameter, and Frequently Asked Questions.
2020.09.28 20.3 19.4.0
  • Updated and renamed the Configuring Single or Dual Lanes section to Transceiver Lane Configurations.
  • Added pin assignments for Bitec FMC revision 10 in the Transceiver Lane Configurations section.
  • Updated the pin assignments for Bitec FMC revision 8 or earlier, and revision 11 with transceiver Avalon® memory-mapped interface group information in the Transceiver Lane Configurations section.
2020.04.13 20.1 19.3.0
  • Updated the Bitec DisplayPort card revision and the IP version in the local parameter in the RTL file at <project directory>/rtl/a10_dp_demo.v and the software config.h file in the Compiling and Testing the Design section.
  • Updated the description for the fmca_la_tx_n_12 signal and added a new signal, fmca_la_tx_p_14 for DisplayPort FMC daughter card pins in the Interface Signals and Parameters section for DisplayPort loopback design examples.
  • Replaced the description about the Parade Tech PS8460 Retimer signals with the FMC On-board Retimer Reconfiguration Interface signals in the Interface Signals and Parameters section for DisplayPort loopback design examples.
  • Added information about the HDCP design example in the HDCP Over DisplayPort Design Examples section. This information is removed from the DisplayPort Intel® FPGA IP User Guide.
2019.07.30 19.2 19.1.0
  • Added information about the DisplayPort MST parallel loopback with and without a PCR module design examples in the DisplayPort Intel® FPGA IP Design Example Quick Start Guide section.
  • Updated the files and folders in the Directory Structure section.
  • Added support for the Bitec DisplayPort FMC daughter card revision 11 in the Hardware and Software Requirements section.
  • Added information about the DisplayPort MST parallel loopback with and without a PCR module design examples in the Generating the Design, DisplayPort Intel® FPGA IP Design Example Parameters, and DisplayPort Intel® FPGA IP Design Example Detailed Description sections.
  • Updated the Regenerating ELF File section to include information about WSL and provided a link to the Nios II Software Developer Handbook.
  • Updated the Compiling and Testing the Design section to include information about the Bitec DisplayPort FMC daughter card revision 11 and channel mapping.
  • Updated the Configuring Single or Dual Lanes section with information about the Bitec DisplayPort FMC daughter card revision 11.
2019.04.05 19.1 19.1
  • Renamed Intel FPGA DisplayPort to DisplayPort Intel® FPGA IP .
  • Updated the Directory Structure section to add the Xcelium* Parallel simulator files.
  • Added instructions to run simulation using the Xcelium* Parallel simulator in the Simulation the Design section.
  • Edited the DisplayPort Design Example Supported EDA Simulators table in the Simulation Testbench section to include Xcelium* Parallel simulator and the supported platforms.
  • Removed the /altera_avalon_i2c file from the Directory Structure section. It is not added in the core folder.
  • Moved the .c and .h software files to a new folder in the Directory Structure section. These files are now in the dp_demo subfolder in version 19.1 of the DisplayPort Intel® FPGA IP .
  • Updated the Bitec DisplayPort FMC daughter card local parameter in the Compiling and Testing the Design section.
  • Edited the note about CRC calculation in the Simulation Testbench section. To ensure CRC is calculated, you must enable the Support CTS test automation parameter.
  • Updated the frequency rate for HBR quad symbols per clock to 67.5 for the RX and TX Transceiver Clockout descriptions in the Clocking Scheme section.
  • Added the Intel® Arria® 10 DisplayPort SST Parallel Loopback with Adaptive Sync Support section to provide guidelines to add the Adaptive Sync feature,
  • Added the Configuring Single or Dual Lanes section to provide guidelines to make the correct pin assignments for single and dual lanes.
  • Added a link to AN 883: Intel Arria 10 DisplayPort TX-only Design in the Creating RX-only or TX-only Designs section. This application note provides information about how to create TX-only designs to transmit 4Kp60 video output generated by the Test Pattern Generator II Intel FPGA IP.
Date Version Changes
November 2017 2017.11.06
  • Renamed DisplayPort IP core to Intel FPGA DisplayPort IP as per Intel rebranding.
  • Changed the term Qsys to Platform Designer.
  • Renamed the design examples to DisplayPort SST Parallel Loopback With PCR and DisplayPort SST Parallel Loopback Without PCR.
  • Updated information that the Intel FPGA DisplayPort IP core now conforms to VESA DisplayPort Standard version 1.4.
  • Added data link rate support for HBR3 (8.10 Gbps). This rate is available only in quad symbols per clock for Intel® Arria® 10 devices in Intel® Quartus® Prime Pro Edition.
  • Added new pins for DisplayPort FMC Daughter Card Pins on FMC Port A.
  • Added a link for workaround to avoid jitter of PLL cascading or non-dedicated clock paths for Intel® Arria® 10 PLL reference clock.
May 2017 2017.05.08
  • Rebranded as Intel.
  • Changed the part number.
  • Added files designated for Intel® Quartus® Prime Pro Edition.
  • Added information for a new design example variant: Arria 10 DP SST Parallel Loopback Without PCR.
  • Added information about the new TX video image interface.
  • Edited the function description for USER_LED[5:1]. The actual lane count should be 4'b0010 = 2 lanes and 4'b0100 = 4 lanes.
  • Added information about DisplayPort transceiver reconfiguration flow.
  • Added guidelines to regenerate .elf file.
  • Added link to archived version of the Arria 10 DisplayPort IP Core Design Example User Guide.
October 2016 2016.10.31 Initial release.
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