DisplayPort Intel® Arria 10 FPGA IP Design Example User Guide

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ID 683050
Date 11/12/2021
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Document Table of Contents
Document Table of Contents x
1. DisplayPort Intel® FPGA IP Design Example Quick Start Guide 2. Parallel Loopback Design Examples 3. HDCP Over DisplayPort Design Example for Intel® Arria® 10 Devices 4. DisplayPort Intel® Arria® 10 FPGA IP Design Example User Guide Archives 5. Revision History for DisplayPort Intel® Arria® 10 FPGA IP Design Example User Guide
1. DisplayPort Intel® FPGA IP Design Example Quick Start Guide x
1.1. Directory Structure 1.2. Hardware and Software Requirements 1.3. Generating the Design 1.4. Simulating the Design 1.5. Compiling and Testing the Design 1.6. DisplayPort Intel® FPGA IP Design Example Parameters
1.5. Compiling and Testing the Design x
1.5.1. Regenerating ELF File
2. Parallel Loopback Design Examples x
2.1. Intel® Arria® 10 DisplayPort SST Parallel Loopback Design Features 2.2. Intel® Arria® 10 DisplayPort MST Parallel Loopback Design Features 2.3. Enabling Adaptive Sync Support 2.4. Creating RX-Only or TX-Only Designs 2.5. Design Components 2.6. Clocking Scheme 2.7. Interface Signals and Parameters 2.8. Hardware Setup 2.9. Simulation Testbench 2.10. DisplayPort Transceiver Reconfiguration Flow 2.11. Transceiver Lane Configurations
3. HDCP Over DisplayPort Design Example for Intel® Arria® 10 Devices x
3.1. High-bandwidth Digital Content Protection (HDCP) 3.2. HDCP Over DisplayPort Design Example Architecture 3.3. Nios II Processor Software Flow 3.4. Design Walkthrough 3.5. Protection of Encryption Key Embedded in FPGA Design 3.6. Debug Guidelines
3.4. Design Walkthrough x
3.4.1. Set Up the Hardware 3.4.2. Generate the Design 3.4.3. Include HDCP Production Keys 3.4.4. Compile the Design 3.4.5. View the Results
3.4.3. Include HDCP Production Keys x
3.4.3.1. Store plain HDCP production keys in the FPGA (Support HDCP Key Management = 0) 3.4.3.2. Store encrypted HDCP production keys in the external flash memory or EEPROM (Support HDCP Key Management = 1)
3.4.3.1. Store plain HDCP production keys in the FPGA (Support HDCP Key Management = 0) x
3.4.3.1.1. HDCP Key Mapping from DCP Key Files 3.4.3.1.2. hdcp1x_tx_kmem.v and hdcp1x_rx_kmem.v files 3.4.3.1.3. hdcp2x_rx_kmem.v file 3.4.3.1.4. hdcp2x_tx_kmem.v file
3.4.3.2. Store encrypted HDCP production keys in the external flash memory or EEPROM (Support HDCP Key Management = 1) x
3.4.3.2.1. Intel KEYENC 3.4.3.2.2. Key Programmer
3.4.5. View the Results x
3.4.5.1. LED Functions
3.5. Protection of Encryption Key Embedded in FPGA Design x
3.5.1. Security Considerations
3.6. Debug Guidelines x
3.6.1. HDCP Status Signals 3.6.2. Modifying HDCP Software Parameters 3.6.3. Frequently Asked Questions (FAQ)
1. DisplayPort Intel® FPGA IP Design Example Quick Start Guide
2. Parallel Loopback Design Examples
3. HDCP Over DisplayPort Design Example for Intel® Arria® 10 Devices
4. DisplayPort Intel® Arria® 10 FPGA IP Design Example User Guide Archives
5. Revision History for DisplayPort Intel® Arria® 10 FPGA IP Design Example User Guide

3.1. High-bandwidth Digital Content Protection (HDCP)

High-bandwidth Digital Content Protection (HDCP) is a form of digital rights protection to create a secure connection between the source to the display.

Intel created the original technology, which is licensed by the Digital Content Protection LLC group. HDCP is a copy protection method where the audio/video stream is encrypted between the transmitter and the receiver, protecting it against illegal copying.

The HDCP features adheres to HDCP Specification version 1.3 and HDCP Specification version 2.3.

The HDCP 1.3 and HDCP 2.3 IPs perform all computation within the hardware core logic with no confidential values (such as private key and session key) being accessible from outside the encrypted IP.

Table 29.  HDCP IP Functions
HDCP IP Functions
HDCP 1.3 IP
  • Authentication exchange
    • Computation of master key (Km)
    • Generation of random An
    • Computation of session key (Ks), M0 and R0.
  • Authentication with repeater
    • Computation and verification of V and V’
  • Link integrity verification
    • Computation of frame key (Ki), Mi and Ri.
  • All cipher modes including hdcpBlockCipher, hdcpStreamCipher, hdcpRekeyCipher, and hdcpRngCipher
  • True random number generator (TRNG)
    • Hardware based, full digital implementation and non-deterministic random number generator
HDCP 2.3 IP
  • Master Key (km), Session Key (ks) and nonce (rn, riv) generation
    • Compliant to NIST.SP800-90A random number generation
  • Authentication and key exchange
    • Generation of random numbers for rtx and rrx compliant to NIST.SP800-90A random number generation
    • Signature verification of receiver certificate (certrx) using DCP public key (kpubdcp)
    • 3072 bits RSASSA-PKCS#1 v1.5
    • RSAES-OAEP (PKCS#1 v2.1) encryption and decryption of Master Key (km)
    • Derivation of kd (dkey0, dkey1) using AES-CTR mode
    • Computation and verification of H and H’
    • Computation of Ekh(km) and km (pairing)
  • Authentication with repeater
    • Computation and verification of V and V’
    • Computation and verification of M and M’
  • System renewability (SRM)
    • SRM signature verification using kpubdcp
    • 3072 bits RSASSA-PKCS#1 v1.5
  • Session Key exchange
  • Generation and computation of Edkey(ks) and riv.
  • Derivation of dkey2 using AES-CTR mode
  • Locality Check
    • Computation and verification of L and L’
    • Generation of nonce (rn)
  • Data stream management
    • AES-CTR mode based key stream generation
  • Asymmetric crypto algorithms
    • RSA with modulus length of 1024 (kpubrx) and 3072 (kpubdcp) bits
    • RSA-CRT (Chinese Remainder Theorem) with modulus length of 512 (kprivrx) bits and exponent length of 512 (kprivrx) bits
  • Low-level cryptographic function
    • Symmetric crypto algorithms
      • AES-CTR mode with a key length of 128 bits
    • Hash, MGF and HMAC algorithms
      • SHA256
      • HMAC-SHA256
      • MGF1-SHA256
    • True random number generator (TRNG)
      • NIST.SP800-90A compliant
      • Hardware based, full digital implementation and non-deterministic random number generator
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