DisplayPort Intel® Arria 10 FPGA IP Design Example User Guide

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ID 683050
Date 11/12/2021
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Document Table of Contents
Document Table of Contents x
1. DisplayPort Intel® FPGA IP Design Example Quick Start Guide 2. Parallel Loopback Design Examples 3. HDCP Over DisplayPort Design Example for Intel® Arria® 10 Devices 4. DisplayPort Intel® Arria® 10 FPGA IP Design Example User Guide Archives 5. Revision History for DisplayPort Intel® Arria® 10 FPGA IP Design Example User Guide
1. DisplayPort Intel® FPGA IP Design Example Quick Start Guide x
1.1. Directory Structure 1.2. Hardware and Software Requirements 1.3. Generating the Design 1.4. Simulating the Design 1.5. Compiling and Testing the Design 1.6. DisplayPort Intel® FPGA IP Design Example Parameters
1.5. Compiling and Testing the Design x
1.5.1. Regenerating ELF File
2. Parallel Loopback Design Examples x
2.1. Intel® Arria® 10 DisplayPort SST Parallel Loopback Design Features 2.2. Intel® Arria® 10 DisplayPort MST Parallel Loopback Design Features 2.3. Enabling Adaptive Sync Support 2.4. Creating RX-Only or TX-Only Designs 2.5. Design Components 2.6. Clocking Scheme 2.7. Interface Signals and Parameters 2.8. Hardware Setup 2.9. Simulation Testbench 2.10. DisplayPort Transceiver Reconfiguration Flow 2.11. Transceiver Lane Configurations
3. HDCP Over DisplayPort Design Example for Intel® Arria® 10 Devices x
3.1. High-bandwidth Digital Content Protection (HDCP) 3.2. HDCP Over DisplayPort Design Example Architecture 3.3. Nios II Processor Software Flow 3.4. Design Walkthrough 3.5. Protection of Encryption Key Embedded in FPGA Design 3.6. Debug Guidelines
3.4. Design Walkthrough x
3.4.1. Set Up the Hardware 3.4.2. Generate the Design 3.4.3. Include HDCP Production Keys 3.4.4. Compile the Design 3.4.5. View the Results
3.4.3. Include HDCP Production Keys x
3.4.3.1. Store plain HDCP production keys in the FPGA (Support HDCP Key Management = 0) 3.4.3.2. Store encrypted HDCP production keys in the external flash memory or EEPROM (Support HDCP Key Management = 1)
3.4.3.1. Store plain HDCP production keys in the FPGA (Support HDCP Key Management = 0) x
3.4.3.1.1. HDCP Key Mapping from DCP Key Files 3.4.3.1.2. hdcp1x_tx_kmem.v and hdcp1x_rx_kmem.v files 3.4.3.1.3. hdcp2x_rx_kmem.v file 3.4.3.1.4. hdcp2x_tx_kmem.v file
3.4.3.2. Store encrypted HDCP production keys in the external flash memory or EEPROM (Support HDCP Key Management = 1) x
3.4.3.2.1. Intel KEYENC 3.4.3.2.2. Key Programmer
3.4.5. View the Results x
3.4.5.1. LED Functions
3.5. Protection of Encryption Key Embedded in FPGA Design x
3.5.1. Security Considerations
3.6. Debug Guidelines x
3.6.1. HDCP Status Signals 3.6.2. Modifying HDCP Software Parameters 3.6.3. Frequently Asked Questions (FAQ)
1. DisplayPort Intel® FPGA IP Design Example Quick Start Guide
2. Parallel Loopback Design Examples
3. HDCP Over DisplayPort Design Example for Intel® Arria® 10 Devices
4. DisplayPort Intel® Arria® 10 FPGA IP Design Example User Guide Archives
5. Revision History for DisplayPort Intel® Arria® 10 FPGA IP Design Example User Guide

2.2. Intel® Arria® 10 DisplayPort MST Parallel Loopback Design Features

The MST parallel loopback design examples demonstrate the transmission of two to four video streams from DisplayPort sink to DisplayPort source with or without Pixel Clock Recovery (PCR).
Figure 7.  Intel® Arria® 10 DisplayPort MST Parallel Loopback with PCR
  • In this variant, the DisplayPort source’s parameter, TX_SUPPORT_IM_ENABLE, is turned off and the standard VSYNC/HSYNC/DE video interface is used.
  • Due to the limitation of PLL numbers on the Intel® Arria® 10 board, by default the IP chooses only 1 stream from the input streams and transmits to the Pixel Clock Recovery block. The Test Pattern Generator (TPG) generates the remaining output streams and the streams display 1080p60 color bar image. For example, if the MST maximum stream count is four, one output video stream is chosen to display, and the remaining three video streams show the same image, which is 1080p60 color bar.
  • You can change the video to a different stream using the user_pb[2] push button. Every time you press user_pb[2] , the next video stream displays.
  • The design examples support up to four streams for audio and video data.
  • The MST design examples use fixed EDID and do not support EDID passthrough.
  • You can modify the bandwidth assignment for each stream in the tx_utils.c file.

    stream 0: btc_dptxll_stream_set_pixel_rate(0,0,594000/MST_RX_STREAMS);

    stream 1: btc_dptxll_stream_set_pixel_rate(0,1,594000/MST_RX_STREAMS);

    stream 2: btc_dptxll_stream_set_pixel_rate(0,2,594000/MST_RX_STREAMS);

    stream 3: btc_dptxll_stream_set_pixel_rate(0,3,594000/MST_RX_STREAMS);

  • The maximum resolution supported for 4 stream counts is 1080p60.
Figure 8.  Intel® Arria® 10 DisplayPort MST Parallel Loopback without PCR
  • In this variant, the DisplayPort source’s parameter, TX_SUPPORT_IM_ENABLE, is turned on (“1”) and the video image interface is used.
  • The DisplayPort sink receives video and or audio streaming from external video source such as GPU and decodes it into parallel video interface.
  • The DisplayPort sink video output directly drives the DisplayPort source video interface and encodes to the DisplayPort main link before transmitting to the monitors.
  • The MST design examples support up to four streams for audio and video data.
  • The design examples use fixed EDID and do not support EDID passthrough.
  • The design examples support a total bandwidth of 594 MHz, distributed equally across the streams. For example, if you enable four streams, each stream would be 148.5 MHz.
  • You can modify the bandwidth assignment for each stream in the tx_utils.c file.

    stream 0: btc_dptxll_stream_set_pixel_rate(0,0,594000/MST_RX_STREAMS);

    stream 1: btc_dptxll_stream_set_pixel_rate(0,1,594000/MST_RX_STREAMS);

    stream 2: btc_dptxll_stream_set_pixel_rate(0,2,594000/MST_RX_STREAMS);

    stream 3: btc_dptxll_stream_set_pixel_rate(0,3,594000/MST_RX_STREAMS);

  • The maximum resolution supported for 4 stream counts is 1080p60.
Table 9.  Design Example Variant Comparison
Design Example PCR Module Enable Video Image Interface Adaptive Sync Video Interface
DisplayPort MST parallel loopback with PCR Required No Not supported Standard VSYNC/HSYNC/DE interface (txN_video_in)
DisplayPort MST parallel loopback without PCR Not required Yes Supported Video Image Interface (txN_video_in_im)
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