AN 804: Implementing Analog-to-Digital Converter Multi-Link Designs with Intel® Stratix® 10 JESD204B RX IP Core

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ID 683032
Date 1/16/2020
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Document Table of Contents
Document Table of Contents x
Implementing Analog-to-Digital Converter Multi-Link Designs with Intel® Stratix® 10 JESD204B RX IP Core
Implementing Analog-to-Digital Converter Multi-Link Designs with Intel® Stratix® 10 JESD204B RX IP Core x
ADC- Intel® Stratix® 10 Multi-Link Design Overview ADC- Intel® Stratix® 10 Multi-Link Design Implementation Guidelines Synchronized ADC- Intel® Stratix® 10 Multi-Link Unsynchronized ADC- Intel® Stratix® 10 Multi-Link Migrating the RX Multi-Link Design from Simulation to Synthesis Document Revision History for Implementing Analog-to-Digital Converter Multi-Link Designs with Intel® Stratix® 10 JESD204B RX IP Core
Synchronized ADC- Intel® Stratix® 10 Multi-Link x
Design Simulation Guidelines Design Synthesis Guidelines
Design Simulation Guidelines x
Editing Design Example Platform Designer System for Synchronized ADC- Intel® Stratix® 10 Multi-Link Editing Design Example Top-Level HDL for Synchronized ADC- Intel® Stratix® 10 Multi-Link Editing TX Simulation Model Platform Designer System for Synchronized ADC- Intel® Stratix® 10 Multi-Link Editing TX Simulation Model Top-Level HDL for Synchronized ADC- Intel® Stratix® 10 Multi-Link Editing Simulation Testbench for Synchronized ADC- Intel® Stratix® 10 Multi-Link Adding IP Cores Signals in the Subsequent Links to the Simulation Waveform Updating the Simulation Script Simulating the Multi-Link Design Viewing the Simulation Results
Design Synthesis Guidelines x
Editing Design Example Platform Designer System for Synchronized ADC- Intel® Stratix® 10 Multi-Link Editing Design Example Top-Level HDL for Synchronized ADC- Intel® Stratix® 10 Multi-Link Editing Design Example Top-Level SDC Constraint for Synchronized ADC- Intel® Stratix® 10 Multi-Link Compiling the Design in Intel® Quartus® Prime Software
Unsynchronized ADC- Intel® Stratix® 10 Multi-Link x
Design Simulation Guidelines Design Synthesis Guidelines
Design Simulation Guidelines x
Editing Design Example Platform Designer System for Unsynchronized ADC- Intel® Stratix® 10 Multi-Link Editing Design Example Top-Level HDL for Unsynchronized ADC- Intel® Stratix® 10 Multi-Link Editing TX Simulation Model Platform Designer System for Unsynchronized ADC- Intel® Stratix® 10 Multi-Link Editing TX Simulation Model Top-Level HDL for Unsynchronized ADC- Intel® Stratix® 10 Multi-Link Editing TX Simulation Testbench for Unsynchronized ADC- Intel® Stratix® 10 Multi-Link Adding IP Cores Signals in the Subsequent Links to the Simulation Waveform Updating the Simulation Script Simulating the Multi-Link Design Viewing the Simulation Results
Design Synthesis Guidelines x
Editing Design Example Platform Designer System for Unsynchronized ADC- Intel® Stratix® 10 Multi-Link Editing Design Example Top-Level HDL for Unsynchronized ADC- Intel® Stratix® 10 Multi-Link Editing Design Example Top-Level SDC Constraint for Unsynchronized ADC- Intel® Stratix® 10 Multi-Link Compiling the Design in Intel® Quartus® Prime Software
Migrating the RX Multi-Link Design from Simulation to Synthesis x
Migrating RX Platform Designer System for Simulation to RX Platform Designer System for Synthesis Migrating RX Top-Level HDL for Simulation to RX Top-Level HDL for Synthesis
Implementing Analog-to-Digital Converter Multi-Link Designs with Intel® Stratix® 10 JESD204B RX IP Core

Updating the Simulation Script

Because of the additional JESD204B IP cores and connection changes in the Platform Designer system, some of the generated Platform Designer filenames are changed. These includes the filenames of the components within the Platform Designer interconnect. The simulation scripts must be updated to avoid elaboration error during the simulation. The simulation script for each simulator is located at the ed_sim/testbench/setup_scripts folder.

The ip-make-simscript utility is used to generate the combined simulation scripts for multiple IP cores, custom components and Platform Designer systems. Specify all Simulation Package Descriptor files (.spd), each of which lists the required simulation files for the corresponding IP core, custom component or Platform Designer system. The IP parameter editor generates the .spd files.

The syntax of this utility is: 

ip-make-simscript --spd=<your_ip.spd> --spd=<your_ip.spd> --output_directory=<your directory>

Download the design example from Design Store and extract the jesd204b_sim.sh for a sample of the shell script that contains the ip-make-simscript utility. The custom.spd file contains entries for custom components such as transport layers, RX top-level, TX top-level and testbench.

Follow these steps to generate an updated list of the Platform Designer interconnect components simulation script:

  1. Place the jesd204b_sim.sh and custom.spd files at the ed_sim/testbench folder.
  2. Back-up the setup_scripts folder. The simulation scripts within the setup_scripts folder are overwritten when jesd204b_sim.sh script is executed.
  3. Launch a Nios® II command shell in Intel® Quartus® Prime software.
  4. Navigate to ed_sim/testbench folder.
  5. At the shell prompt, type the following command:
    ./jesd204b_sim.sh
  6. The simulation script for each simulator is updated in the setup_scripts folder.
Note: If you add custom components to the multi-link design, register your custom components RTL source files into the custom.spd file. If you add components to the Platform Designer system, add the .spd files paths to the ip-make-simscript utility in the jesd204b_sim.sh script.
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