AN 804: Implementing Analog-to-Digital Converter Multi-Link Designs with Intel® Stratix® 10 JESD204B RX IP Core

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ID 683032
Date 1/16/2020
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Document Table of Contents
Document Table of Contents x
Implementing Analog-to-Digital Converter Multi-Link Designs with Intel® Stratix® 10 JESD204B RX IP Core
Implementing Analog-to-Digital Converter Multi-Link Designs with Intel® Stratix® 10 JESD204B RX IP Core x
ADC- Intel® Stratix® 10 Multi-Link Design Overview ADC- Intel® Stratix® 10 Multi-Link Design Implementation Guidelines Synchronized ADC- Intel® Stratix® 10 Multi-Link Unsynchronized ADC- Intel® Stratix® 10 Multi-Link Migrating the RX Multi-Link Design from Simulation to Synthesis Document Revision History for Implementing Analog-to-Digital Converter Multi-Link Designs with Intel® Stratix® 10 JESD204B RX IP Core
Synchronized ADC- Intel® Stratix® 10 Multi-Link x
Design Simulation Guidelines Design Synthesis Guidelines
Design Simulation Guidelines x
Editing Design Example Platform Designer System for Synchronized ADC- Intel® Stratix® 10 Multi-Link Editing Design Example Top-Level HDL for Synchronized ADC- Intel® Stratix® 10 Multi-Link Editing TX Simulation Model Platform Designer System for Synchronized ADC- Intel® Stratix® 10 Multi-Link Editing TX Simulation Model Top-Level HDL for Synchronized ADC- Intel® Stratix® 10 Multi-Link Editing Simulation Testbench for Synchronized ADC- Intel® Stratix® 10 Multi-Link Adding IP Cores Signals in the Subsequent Links to the Simulation Waveform Updating the Simulation Script Simulating the Multi-Link Design Viewing the Simulation Results
Design Synthesis Guidelines x
Editing Design Example Platform Designer System for Synchronized ADC- Intel® Stratix® 10 Multi-Link Editing Design Example Top-Level HDL for Synchronized ADC- Intel® Stratix® 10 Multi-Link Editing Design Example Top-Level SDC Constraint for Synchronized ADC- Intel® Stratix® 10 Multi-Link Compiling the Design in Intel® Quartus® Prime Software
Unsynchronized ADC- Intel® Stratix® 10 Multi-Link x
Design Simulation Guidelines Design Synthesis Guidelines
Design Simulation Guidelines x
Editing Design Example Platform Designer System for Unsynchronized ADC- Intel® Stratix® 10 Multi-Link Editing Design Example Top-Level HDL for Unsynchronized ADC- Intel® Stratix® 10 Multi-Link Editing TX Simulation Model Platform Designer System for Unsynchronized ADC- Intel® Stratix® 10 Multi-Link Editing TX Simulation Model Top-Level HDL for Unsynchronized ADC- Intel® Stratix® 10 Multi-Link Editing TX Simulation Testbench for Unsynchronized ADC- Intel® Stratix® 10 Multi-Link Adding IP Cores Signals in the Subsequent Links to the Simulation Waveform Updating the Simulation Script Simulating the Multi-Link Design Viewing the Simulation Results
Design Synthesis Guidelines x
Editing Design Example Platform Designer System for Unsynchronized ADC- Intel® Stratix® 10 Multi-Link Editing Design Example Top-Level HDL for Unsynchronized ADC- Intel® Stratix® 10 Multi-Link Editing Design Example Top-Level SDC Constraint for Unsynchronized ADC- Intel® Stratix® 10 Multi-Link Compiling the Design in Intel® Quartus® Prime Software
Migrating the RX Multi-Link Design from Simulation to Synthesis x
Migrating RX Platform Designer System for Simulation to RX Platform Designer System for Synthesis Migrating RX Top-Level HDL for Simulation to RX Top-Level HDL for Synthesis
Implementing Analog-to-Digital Converter Multi-Link Designs with Intel® Stratix® 10 JESD204B RX IP Core

ADC- Intel® Stratix® 10 Multi-Link Design Implementation Guidelines

Figure 2. Design Simulation and Synthesis Implementation GuidelinesFollow these set of guidelines to implement your simulation or synthesis ADC- Intel® Stratix® 10 multi-link design.

The following subsections guide you to implement the multi-link design on FPGA. Before you implement the design in the FPGA, you can simulate the design to verify the functionality. You can migrate your simulated design for synthesis and implement the design on the FPGA to interface with ADC. You can follow the synthesis flow guidelines to create the multi-link design for implementation on a FPGA, without performing the simulation.

Here are the steps required to perform simulation and synthesis:

  1. Simulation flow:
    1. Generate the single link JESD204B example design in Intel® Quartus® Prime software.
    2. Simulate the design and confirm the functionality meets your expectation.

      The testbench prints the status of the simulation results.

    3. Modify the RX Platform Designer system to include the additional JESD204B IP cores to form the multi-link.
    4. Modify the RX top-level module to adjust the reset signal connections and to connect the additional JESD204B IP cores to the transport layers and pattern checkers.
    5. Modify the link partner TX Platform Designer system to include the additional JESD204B IP cores to form the multi-link.
    6. Modify the link partner TX top-level module to adjust the reset signal connections and to connect the additional JESD204B IP cores to the transport layers and pattern generators.
    7. Modify the testbench to include additional links.
    8. Optionally, you can add signals to the simulation waveform for the additional links in the multi-link design.
    9. Update the simulation script.
    10. Elaborate and simulate the multi-link design.
    11. Review the simulation results.
  2. Synthesis flow:
    1. Generate the single link JESD204B example design in Intel® Quartus® Prime software.
    2. Modify the RX Platform Designer system to include the additional JESD204B IP cores to form the multi-link.
    3. Modify the RX top-level module to adjust the reset signals connections and to connect the additional JESD204B IP cores to the transport layers and pattern checkers.
    4. Perform pin assignment in the Intel® Quartus® Prime assignment editor.
    5. Modify the timing constraint SDC file to include the additional link or links.
    6. Compile the design in Intel® Quartus® Prime software.
  3. Migration flow from simulation to synthesis:
    1. Modify the RX Platform Designer system to replace Avalon-MM master.
    2. Modify the top-level module to adjust the reset signal connections.
    3. Perform pin assignment in the Intel® Quartus® Prime assignment editor.
    4. Modify the timing constraint SDC file to include the additional link.
    5. Compile the design in Intel® Quartus® Prime software.
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