AN 804: Implementing Analog-to-Digital Converter Multi-Link Designs with Intel® Stratix® 10 JESD204B RX IP Core

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ID 683032
Date 1/16/2020
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Document Table of Contents
Document Table of Contents x
Implementing Analog-to-Digital Converter Multi-Link Designs with Intel® Stratix® 10 JESD204B RX IP Core
Implementing Analog-to-Digital Converter Multi-Link Designs with Intel® Stratix® 10 JESD204B RX IP Core x
ADC- Intel® Stratix® 10 Multi-Link Design Overview ADC- Intel® Stratix® 10 Multi-Link Design Implementation Guidelines Synchronized ADC- Intel® Stratix® 10 Multi-Link Unsynchronized ADC- Intel® Stratix® 10 Multi-Link Migrating the RX Multi-Link Design from Simulation to Synthesis Document Revision History for Implementing Analog-to-Digital Converter Multi-Link Designs with Intel® Stratix® 10 JESD204B RX IP Core
Synchronized ADC- Intel® Stratix® 10 Multi-Link x
Design Simulation Guidelines Design Synthesis Guidelines
Design Simulation Guidelines x
Editing Design Example Platform Designer System for Synchronized ADC- Intel® Stratix® 10 Multi-Link Editing Design Example Top-Level HDL for Synchronized ADC- Intel® Stratix® 10 Multi-Link Editing TX Simulation Model Platform Designer System for Synchronized ADC- Intel® Stratix® 10 Multi-Link Editing TX Simulation Model Top-Level HDL for Synchronized ADC- Intel® Stratix® 10 Multi-Link Editing Simulation Testbench for Synchronized ADC- Intel® Stratix® 10 Multi-Link Adding IP Cores Signals in the Subsequent Links to the Simulation Waveform Updating the Simulation Script Simulating the Multi-Link Design Viewing the Simulation Results
Design Synthesis Guidelines x
Editing Design Example Platform Designer System for Synchronized ADC- Intel® Stratix® 10 Multi-Link Editing Design Example Top-Level HDL for Synchronized ADC- Intel® Stratix® 10 Multi-Link Editing Design Example Top-Level SDC Constraint for Synchronized ADC- Intel® Stratix® 10 Multi-Link Compiling the Design in Intel® Quartus® Prime Software
Unsynchronized ADC- Intel® Stratix® 10 Multi-Link x
Design Simulation Guidelines Design Synthesis Guidelines
Design Simulation Guidelines x
Editing Design Example Platform Designer System for Unsynchronized ADC- Intel® Stratix® 10 Multi-Link Editing Design Example Top-Level HDL for Unsynchronized ADC- Intel® Stratix® 10 Multi-Link Editing TX Simulation Model Platform Designer System for Unsynchronized ADC- Intel® Stratix® 10 Multi-Link Editing TX Simulation Model Top-Level HDL for Unsynchronized ADC- Intel® Stratix® 10 Multi-Link Editing TX Simulation Testbench for Unsynchronized ADC- Intel® Stratix® 10 Multi-Link Adding IP Cores Signals in the Subsequent Links to the Simulation Waveform Updating the Simulation Script Simulating the Multi-Link Design Viewing the Simulation Results
Design Synthesis Guidelines x
Editing Design Example Platform Designer System for Unsynchronized ADC- Intel® Stratix® 10 Multi-Link Editing Design Example Top-Level HDL for Unsynchronized ADC- Intel® Stratix® 10 Multi-Link Editing Design Example Top-Level SDC Constraint for Unsynchronized ADC- Intel® Stratix® 10 Multi-Link Compiling the Design in Intel® Quartus® Prime Software
Migrating the RX Multi-Link Design from Simulation to Synthesis x
Migrating RX Platform Designer System for Simulation to RX Platform Designer System for Synthesis Migrating RX Top-Level HDL for Simulation to RX Top-Level HDL for Synthesis
Implementing Analog-to-Digital Converter Multi-Link Designs with Intel® Stratix® 10 JESD204B RX IP Core

Editing TX Simulation Model Top-Level HDL for Unsynchronized ADC- Intel® Stratix® 10 Multi-Link

The generate statement in the Verilog HDL file uses the LINK system parameter as an index variable to generate the requisite number of instances for the multi-link use case.
  1. Open the top-level HDL file (altera_jesd204_ed_TX.sv) in a text editor.
  2. Modify the LINK system parameter to reflect the number of links in your design.
  3. Insert the newly exported ports from the Platform Designer system at the Platform Designer system instantiation.
  4. Follow these steps to make the connections for the Platform Designer ports:
    1. For SYNC_N, scale up the dimension of sync_n_in port to match with the number of links.
      Example: 
      input wire [LINK-1:0] sync_n_in,
    2. Leave the following ports unconnected:
      • csr_tx_testpattern_a
      • csr_tx_testpattern_b
      • csr_tx_testpattern_c
      • csr_tx_testpattern_d
      • jesd204_tx_dlb_data
      • jesd204_tx_dlb_kchar_data
      • jesd204_tx_link_ready
      • jesd204_tx_somf
      • reset_seq_irq
    3. For the exported ports, increase the index of the wires from 0 to 1 and subsequent numbers for the subsequent links.
      For example, jesd204_rx_link_data[1] wire should be connected to link 1 IP core and transport layer.
  5. Follow these steps to make connections for the pll_cal_busy port:
    1. Create a wire for the pll_cal_busy port: 
      wire       pll_cal_busy;
    2. Distribute the pll_cal_busy port from xcvr_atx_pll_0 to the xcvr_reset_control_0_pll_cal_busy port of each altera_jesd204_subsystem_TX. At the Platform Designer system instantiation: 
      .xcvr_atx_pll_0_pll_cal_busy_pll_cal_busy   (pll_cal_busy),
.altera_jesd204_subsystem_TX_xcvr_reset_control_0_pll_cal_busy_pll_cal_busy   (pll_cal_busy),
.altera_jesd204_subsystem_TX1_xcvr_reset_control_0_pll_cal_busy_pll_cal_busy   (pll_cal_busy),
  6. Because of there is only one TX PLL for all the IP cores, copy the transceiver PLL locked status pin for link 1 IP core. 
    generate
	for (i=1; i<LINK; i=i+1) begin: XCVR_PLL_LOCKED
		assign xcvr_pll_locked[i] = xcvr_pll_locked[0];
	end		
endgenerate
  7. Save the top-level HDL file changes.
Level Two Title