AN 804: Implementing Analog-to-Digital Converter Multi-Link Designs with Intel® Stratix® 10 JESD204B RX IP Core

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ID 683032
Date 1/16/2020
Public
Document Table of Contents
Document Table of Contents x
Implementing Analog-to-Digital Converter Multi-Link Designs with Intel® Stratix® 10 JESD204B RX IP Core
Implementing Analog-to-Digital Converter Multi-Link Designs with Intel® Stratix® 10 JESD204B RX IP Core x
ADC- Intel® Stratix® 10 Multi-Link Design Overview ADC- Intel® Stratix® 10 Multi-Link Design Implementation Guidelines Synchronized ADC- Intel® Stratix® 10 Multi-Link Unsynchronized ADC- Intel® Stratix® 10 Multi-Link Migrating the RX Multi-Link Design from Simulation to Synthesis Document Revision History for Implementing Analog-to-Digital Converter Multi-Link Designs with Intel® Stratix® 10 JESD204B RX IP Core
Synchronized ADC- Intel® Stratix® 10 Multi-Link x
Design Simulation Guidelines Design Synthesis Guidelines
Design Simulation Guidelines x
Editing Design Example Platform Designer System for Synchronized ADC- Intel® Stratix® 10 Multi-Link Editing Design Example Top-Level HDL for Synchronized ADC- Intel® Stratix® 10 Multi-Link Editing TX Simulation Model Platform Designer System for Synchronized ADC- Intel® Stratix® 10 Multi-Link Editing TX Simulation Model Top-Level HDL for Synchronized ADC- Intel® Stratix® 10 Multi-Link Editing Simulation Testbench for Synchronized ADC- Intel® Stratix® 10 Multi-Link Adding IP Cores Signals in the Subsequent Links to the Simulation Waveform Updating the Simulation Script Simulating the Multi-Link Design Viewing the Simulation Results
Design Synthesis Guidelines x
Editing Design Example Platform Designer System for Synchronized ADC- Intel® Stratix® 10 Multi-Link Editing Design Example Top-Level HDL for Synchronized ADC- Intel® Stratix® 10 Multi-Link Editing Design Example Top-Level SDC Constraint for Synchronized ADC- Intel® Stratix® 10 Multi-Link Compiling the Design in Intel® Quartus® Prime Software
Unsynchronized ADC- Intel® Stratix® 10 Multi-Link x
Design Simulation Guidelines Design Synthesis Guidelines
Design Simulation Guidelines x
Editing Design Example Platform Designer System for Unsynchronized ADC- Intel® Stratix® 10 Multi-Link Editing Design Example Top-Level HDL for Unsynchronized ADC- Intel® Stratix® 10 Multi-Link Editing TX Simulation Model Platform Designer System for Unsynchronized ADC- Intel® Stratix® 10 Multi-Link Editing TX Simulation Model Top-Level HDL for Unsynchronized ADC- Intel® Stratix® 10 Multi-Link Editing TX Simulation Testbench for Unsynchronized ADC- Intel® Stratix® 10 Multi-Link Adding IP Cores Signals in the Subsequent Links to the Simulation Waveform Updating the Simulation Script Simulating the Multi-Link Design Viewing the Simulation Results
Design Synthesis Guidelines x
Editing Design Example Platform Designer System for Unsynchronized ADC- Intel® Stratix® 10 Multi-Link Editing Design Example Top-Level HDL for Unsynchronized ADC- Intel® Stratix® 10 Multi-Link Editing Design Example Top-Level SDC Constraint for Unsynchronized ADC- Intel® Stratix® 10 Multi-Link Compiling the Design in Intel® Quartus® Prime Software
Migrating the RX Multi-Link Design from Simulation to Synthesis x
Migrating RX Platform Designer System for Simulation to RX Platform Designer System for Synthesis Migrating RX Top-Level HDL for Simulation to RX Top-Level HDL for Synthesis
Implementing Analog-to-Digital Converter Multi-Link Designs with Intel® Stratix® 10 JESD204B RX IP Core

Editing Design Example Top-Level SDC Constraint for Synchronized ADC- Intel® Stratix® 10 Multi-Link

For every SDC constraint in the set multicycle path section, add SDC constraint for the newly added IP cores and pattern checkers.

Top-level SDC Constraint:

set_multicycle_path -end -setup -from [get_cells -compatibility_mode u_altera_jesd204_ed_qsys_RX|altera_jesd204_subsystem_rx|<IP core instance name>| altera_jesd204_rx|inst_rx|altera_jesd204_rx_csr_inst|rx_test_inst|sync[*].u|dreg[0]] -to [get_cells -compatibility_mode GEN_BLOCK[<i>].u_chk|prbs_in_Nbit[*]] 2

set_multicycle_path -end -hold -from [get_cells -compatibility_mode u_altera_jesd204_ed_qsys_RX|altera_jesd204_subsystem_rx|<IP core instance name>|altera_jesd204_rx|inst_rx|altera_jesd204_rx_csr_inst|rx_test_inst|sync[*].u|dreg[0]] -to [get_cells -compatibility_mode GEN_BLOCK[<i>].u_chk|prbs_in_Nbit[*]] 1

<ip core instance name> is the name for the duplicated copy of the altera_jesd204_RX IP core that you name in 3.

<i> is the index number of generation loop.

The following example has the newly added design entities:

set_multicycle_path -end -setup -from [get_cells -compatibility_mode u_altera_jesd204_ed_qsys_RX|altera_jesd204_subsystem_rx|altera_jesd204_rx1|altera_jesd204_rx|inst_rx|altera_jesd204_rx_csr_inst|rx_test_inst|sync[*].u|dreg[0]] -to [get_cells -compatibility_mode GEN_BLOCK[1].u_chk|prbs_in_Nbit[*]] 2
set_multicycle_path -end -hold -from [get_cells -compatibility_mode u_altera_jesd204_ed_qsys_RX|altera_jesd204_subsystem_rx|altera_jesd204_rx1|altera_jesd204_rx|inst_rx|altera_jesd204_rx_csr_inst|rx_test_inst|sync[*].u|dreg[0]] -to [get_cells -compatibility_mode GEN_BLOCK[1].u_chk|prbs_in_Nbit[*]] 1
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