AN 804: Implementing Analog-to-Digital Converter Multi-Link Designs with Intel® Stratix® 10 JESD204B RX IP Core

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ID 683032
Date 1/16/2020
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Document Table of Contents
Document Table of Contents x
Implementing Analog-to-Digital Converter Multi-Link Designs with Intel® Stratix® 10 JESD204B RX IP Core
Implementing Analog-to-Digital Converter Multi-Link Designs with Intel® Stratix® 10 JESD204B RX IP Core x
ADC- Intel® Stratix® 10 Multi-Link Design Overview ADC- Intel® Stratix® 10 Multi-Link Design Implementation Guidelines Synchronized ADC- Intel® Stratix® 10 Multi-Link Unsynchronized ADC- Intel® Stratix® 10 Multi-Link Migrating the RX Multi-Link Design from Simulation to Synthesis Document Revision History for Implementing Analog-to-Digital Converter Multi-Link Designs with Intel® Stratix® 10 JESD204B RX IP Core
Synchronized ADC- Intel® Stratix® 10 Multi-Link x
Design Simulation Guidelines Design Synthesis Guidelines
Design Simulation Guidelines x
Editing Design Example Platform Designer System for Synchronized ADC- Intel® Stratix® 10 Multi-Link Editing Design Example Top-Level HDL for Synchronized ADC- Intel® Stratix® 10 Multi-Link Editing TX Simulation Model Platform Designer System for Synchronized ADC- Intel® Stratix® 10 Multi-Link Editing TX Simulation Model Top-Level HDL for Synchronized ADC- Intel® Stratix® 10 Multi-Link Editing Simulation Testbench for Synchronized ADC- Intel® Stratix® 10 Multi-Link Adding IP Cores Signals in the Subsequent Links to the Simulation Waveform Updating the Simulation Script Simulating the Multi-Link Design Viewing the Simulation Results
Design Synthesis Guidelines x
Editing Design Example Platform Designer System for Synchronized ADC- Intel® Stratix® 10 Multi-Link Editing Design Example Top-Level HDL for Synchronized ADC- Intel® Stratix® 10 Multi-Link Editing Design Example Top-Level SDC Constraint for Synchronized ADC- Intel® Stratix® 10 Multi-Link Compiling the Design in Intel® Quartus® Prime Software
Unsynchronized ADC- Intel® Stratix® 10 Multi-Link x
Design Simulation Guidelines Design Synthesis Guidelines
Design Simulation Guidelines x
Editing Design Example Platform Designer System for Unsynchronized ADC- Intel® Stratix® 10 Multi-Link Editing Design Example Top-Level HDL for Unsynchronized ADC- Intel® Stratix® 10 Multi-Link Editing TX Simulation Model Platform Designer System for Unsynchronized ADC- Intel® Stratix® 10 Multi-Link Editing TX Simulation Model Top-Level HDL for Unsynchronized ADC- Intel® Stratix® 10 Multi-Link Editing TX Simulation Testbench for Unsynchronized ADC- Intel® Stratix® 10 Multi-Link Adding IP Cores Signals in the Subsequent Links to the Simulation Waveform Updating the Simulation Script Simulating the Multi-Link Design Viewing the Simulation Results
Design Synthesis Guidelines x
Editing Design Example Platform Designer System for Unsynchronized ADC- Intel® Stratix® 10 Multi-Link Editing Design Example Top-Level HDL for Unsynchronized ADC- Intel® Stratix® 10 Multi-Link Editing Design Example Top-Level SDC Constraint for Unsynchronized ADC- Intel® Stratix® 10 Multi-Link Compiling the Design in Intel® Quartus® Prime Software
Migrating the RX Multi-Link Design from Simulation to Synthesis x
Migrating RX Platform Designer System for Simulation to RX Platform Designer System for Synthesis Migrating RX Top-Level HDL for Simulation to RX Top-Level HDL for Synthesis
Implementing Analog-to-Digital Converter Multi-Link Designs with Intel® Stratix® 10 JESD204B RX IP Core

Editing TX Simulation Testbench for Unsynchronized ADC- Intel® Stratix® 10 Multi-Link

The simulation testbench, tb_top.sv is located at ed_sim/testbench/models folder. Follow these steps to edit the testbench.
  1. Open the testbench (tb_top.sv) in a text editor.
  2. Add the LINK parameter at the localparam declaration section. Example: 
    localparam LINK = 2;     // Number of IP core in the multi-link design
  3. Change the dimension of the sync_n wire: 
    wire [LINK-1:0] sync_n;
  4. Scale-up the dimension of the u_altera_jesd204_ed_TX.xcvr_rst_ctrl_tx_ready and u_altera_jesd204_ed_RX.xcvr_rst_ctrl_rx_ready ports as the following: 
    assign xcvr_rst_ctrl_tx_ready = &u_altera_jesd204_ed_TX.xcvr_rst_ctrl_tx_ready[LINK-1:0];
assign xcvr_rst_ctrl_rx_ready = &u_altera_jesd204_ed_RX.xcvr_rst_ctrl_rx_ready[LINK-1:0];
  5. Scale-up the dimension of the u_altera_jesd204_ed_TX.tx_link_rst_n and u_altera_jesd204_ed_RX.rx_link_rst_n ports as the following: 
    assign txlink_rst_n = &u_altera_jesd204_ed_TX.tx_link_rst_n[LINK-1:0];
assign rxlink_rst_n = &u_altera_jesd204_ed_RX.rx_link_rst_n[LINK-1:0];
  6. Change the dimension and assignment of the following wires and registers:
    • reg [LINK-1:0] tx_link_error_reg = {LINK{1’b0}};
    • reg [LINK-1:0] rx_link_error_reg = {LINK{1’b0}};
    • reg [LINK-1:0] data_error_reg = {LINK{1’b0}};
    • wire [LINK*L-1:0] tx_serial_data;
    • wire [LINK*L-1:0] rx_serial_data;
    • wire [LINK-1:0] data_valid;
    • wire [LINK-1:0] data_error;
    • wire [LINK-1:0] tx_link_error;
    • wire [LINK-1:0] rx_link_error;
  7. Create the generation loops for the link error and data error signals: 
    // Pass/Fail Mechanism
   genvar i;
   generate 
      for (i=0; i<LINK; i=i+1) begin: LINK_ERROR	
         // Make sure interrupts do not assert
         always @(posedge mgmt_clk or negedge txlink_rst_n) begin
            if(!txlink_rst_n) 
               tx_link_error_reg[i] <= 1'b0;
            else if (tx_link_error[i])
               tx_link_error_reg[i] <= 1'b1;
            else
               tx_link_error_reg[i] <= tx_link_error_reg[i]; 
         end

         always @(posedge mgmt_clk or negedge rxlink_rst_n) begin
            if(!rxlink_rst_n)
               rx_link_error_reg[i] <= 1'b0;
            else if (rx_link_error[i])
               rx_link_error_reg[i] <= 1'b1;
            else
               rx_link_error_reg[i] <= rx_link_error_reg[i];
         end
      end
   endgenerate	
	
   generate
      for (i=0; i<LINK; i=i+1) begin DATA_ERROR	
	      always @ (posedge data_error[i]) begin
            if (data_valid[i] == 1'b1)
               data_error_reg[i] <= 1'b1;
            end
      end
   endgenerate
  8. To monitor the combined simulation results of the multi-link, modify the test_passed assignment statement so that if IP core in any of the links has interrupt, the simulation reports failure: 
     assign test_passed = (&data_error_reg==1'b0) & (&data_valid==1'b1) & ~(|tx_link_error_reg) & ~(|rx_link_error_reg);
  9. Configure the test mode for the IP cores and link partners in the subsequent links.
    Note: The address in the BFM write/read task consists of base address + IP core register offset. Refer to the Platform Designer address map to set the address in the BFM write/read task for the IP cores in the subsequent links.
    Example: 
    avalon_mm_csr_sim_model_wr(32'h001C00D0, pat_testmode);	// Link 1 CSR
avalon_mm_csr_dut_wr(32'h001D00D0, pat_testmode);		  // Link 1 CSR
  10. Edit the criteria for displaying link error message for data_error_reg, tx_link_error_reg and rx_link_error_reg signals so that if IP core in any of the links has interrupt, the simulation reports failure. Example: 
       if (&data_valid) begin                        
      if (|data_error_reg) begin
         $display("Pattern Checker(s): Data error(s) found!");
      end else begin
         $display("Pattern Checker(s): OK!");
      end       
   end else begin
      $display("Pattern Checker(s): No valid data found!");
   end

  
   if (|tx_link_error_reg) begin
      $display("JESD204B Tx Core(s): Tx link error(s) found!");
   end else begin
      $display("JESD204B Tx Core(s): OK!");
   end

   if (|rx_link_error_reg) begin
      $display("JESD204B Rx Core(s): Rx link error(s) found!");
   end else begin
      $display("JESD204B Rx Core(s): OK!");
   end
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