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ADC- Intel® Stratix® 10 Multi-Link Design Overview
ADC- Intel® Stratix® 10 Multi-Link Design Implementation Guidelines
Synchronized ADC- Intel® Stratix® 10 Multi-Link
Unsynchronized ADC- Intel® Stratix® 10 Multi-Link
Migrating the RX Multi-Link Design from Simulation to Synthesis
Document Revision History for Implementing Analog-to-Digital Converter Multi-Link Designs with Intel® Stratix® 10 JESD204B RX IP Core
Editing Design Example Platform Designer System for Synchronized ADC- Intel® Stratix® 10 Multi-Link
Editing Design Example Top-Level HDL for Synchronized ADC- Intel® Stratix® 10 Multi-Link
Editing TX Simulation Model Platform Designer System for Synchronized ADC- Intel® Stratix® 10 Multi-Link
Editing TX Simulation Model Top-Level HDL for Synchronized ADC- Intel® Stratix® 10 Multi-Link
Editing Simulation Testbench for Synchronized ADC- Intel® Stratix® 10 Multi-Link
Adding IP Cores Signals in the Subsequent Links to the Simulation Waveform
Updating the Simulation Script
Simulating the Multi-Link Design
Viewing the Simulation Results
Editing Design Example Platform Designer System for Synchronized ADC- Intel® Stratix® 10 Multi-Link
Editing Design Example Top-Level HDL for Synchronized ADC- Intel® Stratix® 10 Multi-Link
Editing Design Example Top-Level SDC Constraint for Synchronized ADC- Intel® Stratix® 10 Multi-Link
Compiling the Design in Intel® Quartus® Prime Software
Editing Design Example Platform Designer System for Unsynchronized ADC- Intel® Stratix® 10 Multi-Link
Editing Design Example Top-Level HDL for Unsynchronized ADC- Intel® Stratix® 10 Multi-Link
Editing TX Simulation Model Platform Designer System for Unsynchronized ADC- Intel® Stratix® 10 Multi-Link
Editing TX Simulation Model Top-Level HDL for Unsynchronized ADC- Intel® Stratix® 10 Multi-Link
Editing TX Simulation Testbench for Unsynchronized ADC- Intel® Stratix® 10 Multi-Link
Adding IP Cores Signals in the Subsequent Links to the Simulation Waveform
Updating the Simulation Script
Simulating the Multi-Link Design
Viewing the Simulation Results
Editing Design Example Platform Designer System for Unsynchronized ADC- Intel® Stratix® 10 Multi-Link
Editing Design Example Top-Level HDL for Unsynchronized ADC- Intel® Stratix® 10 Multi-Link
Editing Design Example Top-Level SDC Constraint for Unsynchronized ADC- Intel® Stratix® 10 Multi-Link
Compiling the Design in Intel® Quartus® Prime Software
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Adding IP Cores Signals in the Subsequent Links to the Simulation Waveform
Note: This is an optional step.
You can add the signals of the IP cores in subsequent links to the simulation waveform to monitor the link initialization. For ModelSim‐ Intel® FPGA Edition, include the signals of interest into the tb_top_waveform.do file at ed_sim/testbench/mentor folder. Example:
add wave -noupdate -divider {LINK 1}
add wave -noupdate -group {JESD204B BASE CORE 222 L1} {/tb_top/u_altera_jesd204_ed_RX/u_altera_jesd204_ed_qsys_RX/altera_jesd204_subsystem_rx/altera_jesd204_rx1/alldev_lane_aligned}
add wave -noupdate -group {RX TRANSPORT L1}
{/tb_top/u_altera_jesd204_ed_RX/GEN_BLOCK[1]/u_jesd204b_transport_rx/csr_f}
add wave -noupdate -group {PATTERN CHK L1}
{/tb_top/u_altera_jesd204_ed_RX/GEN_BLOCK[1]/u_chk/avst_datain}