AN 804: Implementing Analog-to-Digital Converter Multi-Link Designs with Intel® Stratix® 10 JESD204B RX IP Core

ID 683032
Date 1/16/2020
Public
Document Table of Contents

Document Revision History for Implementing Analog-to-Digital Converter Multi-Link Designs with Intel® Stratix® 10 JESD204B RX IP Core

Version Changes
2020.01.16
  • Reorganized the topics to separate guidelines for design simulation and design synthesis for synchronized and unsynchronized ADC multi-link designs.
2018.03.09
  • Updated document title AN804: Implementing ADC- Intel® Stratix® 10 Multi-Link Design with JESD204B RX IP Core to AN804: Implementing Analog-to-Digital Converter Multi-Link Designs with Intel® Stratix® 10 JESD204B RX IP Core.
  • Added reconfig_clk, reconfig_reset, and reconfig_avmm ports to Ports for Duplicated IP Core table in Editing Design Example Platform Designer System for Synchronized ADC- Intel® Stratix® 10 Multi-Link.
2018.01.05
  • Added simulation guidelines for synchronized and unsynchronized multi-link design.
  • Added simulation to synthesis migration guidelines.
  • Added design simulation and synthesis overview.
  • Updated instances of Qsys to Platform Designer.
  • Reorganized document structure.
2017.05.08 Initial release.