Visible to Intel only — GUID: bya1488183444724
Ixiasoft
ADC- Intel® Stratix® 10 Multi-Link Design Overview
ADC- Intel® Stratix® 10 Multi-Link Design Implementation Guidelines
Synchronized ADC- Intel® Stratix® 10 Multi-Link
Unsynchronized ADC- Intel® Stratix® 10 Multi-Link
Migrating the RX Multi-Link Design from Simulation to Synthesis
Document Revision History for Implementing Analog-to-Digital Converter Multi-Link Designs with Intel® Stratix® 10 JESD204B RX IP Core
Editing Design Example Platform Designer System for Synchronized ADC- Intel® Stratix® 10 Multi-Link
Editing Design Example Top-Level HDL for Synchronized ADC- Intel® Stratix® 10 Multi-Link
Editing TX Simulation Model Platform Designer System for Synchronized ADC- Intel® Stratix® 10 Multi-Link
Editing TX Simulation Model Top-Level HDL for Synchronized ADC- Intel® Stratix® 10 Multi-Link
Editing Simulation Testbench for Synchronized ADC- Intel® Stratix® 10 Multi-Link
Adding IP Cores Signals in the Subsequent Links to the Simulation Waveform
Updating the Simulation Script
Simulating the Multi-Link Design
Viewing the Simulation Results
Editing Design Example Platform Designer System for Synchronized ADC- Intel® Stratix® 10 Multi-Link
Editing Design Example Top-Level HDL for Synchronized ADC- Intel® Stratix® 10 Multi-Link
Editing Design Example Top-Level SDC Constraint for Synchronized ADC- Intel® Stratix® 10 Multi-Link
Compiling the Design in Intel® Quartus® Prime Software
Editing Design Example Platform Designer System for Unsynchronized ADC- Intel® Stratix® 10 Multi-Link
Editing Design Example Top-Level HDL for Unsynchronized ADC- Intel® Stratix® 10 Multi-Link
Editing TX Simulation Model Platform Designer System for Unsynchronized ADC- Intel® Stratix® 10 Multi-Link
Editing TX Simulation Model Top-Level HDL for Unsynchronized ADC- Intel® Stratix® 10 Multi-Link
Editing TX Simulation Testbench for Unsynchronized ADC- Intel® Stratix® 10 Multi-Link
Adding IP Cores Signals in the Subsequent Links to the Simulation Waveform
Updating the Simulation Script
Simulating the Multi-Link Design
Viewing the Simulation Results
Editing Design Example Platform Designer System for Unsynchronized ADC- Intel® Stratix® 10 Multi-Link
Editing Design Example Top-Level HDL for Unsynchronized ADC- Intel® Stratix® 10 Multi-Link
Editing Design Example Top-Level SDC Constraint for Unsynchronized ADC- Intel® Stratix® 10 Multi-Link
Compiling the Design in Intel® Quartus® Prime Software
Visible to Intel only — GUID: bya1488183444724
Ixiasoft
Document Revision History for Implementing Analog-to-Digital Converter Multi-Link Designs with Intel® Stratix® 10 JESD204B RX IP Core
Version | Changes |
---|---|
2020.01.16 |
|
2018.03.09 |
|
2018.01.05 |
|
2017.05.08 | Initial release. |