AN 804: Implementing Analog-to-Digital Converter Multi-Link Designs with Intel® Stratix® 10 JESD204B RX IP Core
Visible to Intel only — GUID: zug1510420979603
Ixiasoft
Visible to Intel only — GUID: zug1510420979603
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Simulating the Multi-Link Design
After the modification to the altera_jesd204_ed_qsys_RX.qsys, altera_jesd204_ed_RX.sv, altera_jesd204_ed_qsys_TX.qsys, altera_jesd204_ed_TX.sv and tb_top.sv, you are ready to simulate the multi-link design using the simulator of your choice. The following example uses ModelSim‐ Intel® FPGA Edition.
- Launch the ModelSim‐ Intel® FPGA Edition.
- At the File menu, select Change Directory.
- Select ed_sim/testbench/mentor.
- To run the simulation script, type the following command at the transcript prompt:
do run_tb_top.tcl